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Interconnect for semiconductor components and method of fabrication    
United States Patent6130148   
Link to this pagehttp://www.wikipatents.com/6130148.html
Inventor(s)Farnworth; Warren M. (Nampa, ID), Akram; Salman (Boise, ID)
AbstractAn interconnect for electrically contacting semiconductor components such as bare dice, wafers and chip scale packages, is provided. The interconnect includes a rigid substrate and polymer contact members formed on the substrate. The polymer contact members are adapted to electrically engage contacts (e.g., bond pads, solder bumps) on the component. In one embodiment the polymer contact members are raised members with penetrating projections covered with conductive layers. In another embodiment the polymer contact members are indentations and penetrating projections covered with conductive layers. A method for fabricating the polymer contact members includes the steps of depositing, patterning and etching a thick film resist. These steps are followed by electrolessly depositing conductive layers on the contact members, and conductors in electrical communication with the conductive layers.
   














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Drawing from US Patent 6130148
Interconnect for semiconductor components and method of fabrication - US Patent 6130148 Drawing
Interconnect for semiconductor components and method of fabrication
Inventor     Farnworth; Warren M. (Nampa, ID) , Akram; Salman (Boise, ID)
Owner/Assignee    
Patent assignment
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Publication Date     October 10, 2000
Application Number     08/989,444
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     December 12, 1997
US Classification     438/613 257/E23.004 257/E23.067 438/612 438/614
Int'l Classification    
Examiner     Picardat; Kevin M.
Assistant Examiner    
Attorney/Law Firm     Gratton; Stephen A.
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Priority Data    
USPTO Field of Search     438/612 438/613 438/614 438/615
Patent Tags     interconnect semiconductor components fabrication
   
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 U.S. References
 
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6040702
Hembree et al.

Mar,2000

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6040239
Akram et al.

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Akram et al.

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6005288
Farnworth et al.

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Farnworth

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 Technical Review Submit all comments and votes
 Claims Submit all comments and votes
 


What is claimed is:

1. A method for fabricating an interconnect for a semiconductor component having a contact comprising:

providing a substrate;

providing a resist configured to form features with an aspect ratio (height/width) of at least 10;

depositing the resist on the substrate to form a polymer layer;

exposing, etching, and curing the polymer layer to form a raised contact member on the substrate; and

forming a conductive layer on the contact member configured to electrically engage the contact on the component.

2. The method of claim 1 wherein a height of the polymer layer and the contact member is about 3 mils to 10 mils.

3. The method of claim 1 wherein the resist comprises an epoxy, a solvent and a photoinitiator.

4. The method of claim 1 further comprising forming a projection in the polymer layer prior to etching such that the contact member includes the projection for penetrating the contact on the component.

5. A method for fabricating an interconnect for a semiconductor component having a bumped contact comprising:

providing a substrate;

providing a resist configured to form features with an aspect ratio (height/width) of at least 10;

depositing the resist on the substrate to form a polymer layer;

exposing and etching the polymer layer to form an indentation configured to retain the bumped contact on the component;

curing the polymer layer; and

depositing a conductive layer in the indentations.

6. The method of claim 5 wherein the indentation has a death of about 1-5 mils.

7. The method of claim 5 wherein the resist comprises an epoxy, a solvent and a photoinitiator.

8. The method of claim 5 further comprising forming at least one projection in the indentation for penetrating the bumped contact on the component by exposing and etching the polymer layer.

9. A method for fabricating an interconnect for a semiconductor component having a plurality of contacts comprising:

providing a substrate;

providing a resist configured to form features having an aspect ratio (height/width) of at least 10;

depositing the resist on the substrate to form a resist layer with a thickness of about 3 to 10 mils;

exposing the resist layer through openings in a reticle;

etching the resist layer to remove either exposed or unexposed portion of the resist layer to form a plurality of raised contact members corresponding to a pattern of the contacts on the component and having a height corresponding to the thickness; and

forming a conductive layer on each contact member.

10. The method of claim 9 wherein the resist comprises an epoxy, a solvent and a photoinitiator.

11. The method of claim 9 wherein forming the conductive layer comprises an electroless or electrochemical deposition process.

12. The method of claim 9 further comprising forming an insulating layer on the substrate prior to the depositing step and endpointing the etching step on the insulating layer.

13. A method for fabricating an interconnect for a semiconductor component having a bumped contact comprising:

providing a substrate;

providing a resist configured to form features having an aspect ratio (height/width) of at least 10;

depositing the resist on the substrate to form a resist layer;

etching the resist layer to form an indentation therein configured to retain the bumped contact and having a depth of about 1-5 mils;

depositing a conductive layer within the indentation configured to electrically engage the bumped contact; and

forming a conductor on the substrate in electrical communication with the conductive layer.

14. The method of claim 13 wherein the resist comprises an epoxy, a solvent and a photoinitiator.

15. The method of claim 13 wherein the substrate comprises a material selected from the group consisting of ceramic, mullite and silicon.

16. The method of claim 13 wherein the conductive layer comprises a material selected from the group consisting of nickel, palladium and platinum.

17. A method for fabricating an interconnect for a semiconductor component having a contact comprising:

providing a substrate;

providing a resist comprising epoxy and a photoinitiator;

depositing the resist on the substrate to form a resist layer having a thickness;

exposing the resist layer through a reticle;

etching the resist layer to form a contact member on the substrate having a height equal to the thickness; and

depositing a conductive layer on the contact member configured to electrically engage the contact on the component.

18. The method of claim 17 further comprising forming an insulating layer on the substrate and endpointing the etching step on the insulating layer.

19. The method of claim 17 further comprising forming a projection in the resist layer prior to the etching step such that the contact member includes the projection for penetrating the contact on the component.

20. A method for fabricating an interconnect for a semiconductor component having a bumped contact comprising:

providing a substrate;

providing a resist comprising epoxy and a photoinitiator;

depositing the resist on the substrate to form a resist layer;

exposing the resist layer through a reticle;

etching the resist layer to form an indentation therein sized to retain the bumped contact on the component and a projection in the indentation configured to penetrate the bumped contact; and

depositing a conductive layer in the indentation conzfigured to electrically engage the bumped contact.

21. The method of claim 20 wherein the resist is formulated to form features having an aspect ratio (height/width) of at least 10.
 Description Submit all comments and votes
 


FIELD OF THE INVENTION

This invention relates generally to semiconductor manufacture and more particularly to an interconnect for making electrical connections with semiconductor components.

BACKGROUND OF THE INVENTION

Semiconductor dice are used in the construction of electronic components, such as multi chip modules. For example, bare semiconductor dice can be mounted to substrates formed of ceramic and FR-4 materials. Flip chip mounting of bumped dice is one method for electrically connecting the dice to the substrates. With flip chip mounting, solder bumps on the device bond pads are reflowed into electrical contact with contacts on the substrate. Chip on board (COB) mounting of dice to substrates can also be employed. With chip on board mounting, wire bonds are formed between the device bond pads and contacts on the substrate. TAB mounting is another mounting method. With TAB mounting, electrical connections are made to the device bond pads, using a multi layer tape comprising a polymer backing with patterns of conductors.

Chip scale packages are sometimes used in place of bare dice for fabricating electronic components. Typically, a chip scale package includes a substrate bonded to the face of a bare die. The substrate includes the external contacts for making outside electrical connections to the chip scale package. The substrate for a chip scale package can comprise a flexible material, such as a polymer tape, or a rigid material, such as silicon, ceramic, glass or FR-4. The external contacts for one type of chip scale package include solder balls arranged in a dense array, such as a ball grid array (BGA), or a fine ball grid array (FBGA). In general, chip scale packages can be mounted to substrates using the same mounting methods employed with bare dice (e.g., flip chip, COB, TAB).

Besides making permanent electrical connections to bare dice and chip scale packages for fabricating electronic components, electrical connections are sometimes necessary for testing applications. For example, bare dice are tested in the manufacture of known good die (KGD). Chip scale packages must also be tested prior to use in electronic components. In these cases the electrical connections with the device bond pads for bare dice, or with external contacts for chip scale packages, are preferably non-bonded, temporary electrical connections. In addition to being temporary, the electrical connections must have a low contact resistance, and preferably cause minimal damage to the device bond pads or external contacts.

The present invention is directed to an improved interconnect for making electrical connections with semiconductor components including dice and chip scale packages.

SUMMARY OF THE INVENTION

In accordance with the present invention, an improved interconnect for semiconductor components, such as dice, wafers and chip scale packages, and a method for fabricating the interconnect are provided. Also provided are improved test systems employing the interconnect.

The interconnect includes a substrate, and polymer contact members formed on the substrate, adapted to electrically engage contacts on the components. The polymer contact members als