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Description  |
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BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of integrated circuits. More particularly, the invention provides a technique, including a method and apparatus, for the deposition of a reduced-dielectric-constant, fluorine-doped insulating film
in high-aspect-ratio trenches on semiconductor substrates.
One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition (CVD).
Thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film.
The temperature needed for the surface reactions to occur can be reduced if a plasma is formed from the gases within the deposition chamber. Plasma promotes dissociation of the gases by the application of radio frequency (RF) energy to a
reaction zone near the substrate surface, thereby creating a plasma of reactive species. The reactivity of the plasma species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such CVD
processes.
The relatively low temperature of a plasma CVD process makes such a process ideal for the formation of insulating layers over deposited metal layers and for the formation of other insulating layers. In fact, while higher temperatures generally
result in a higher deposition rate in thermal CVD processes, lower temperatures may result in higher deposition rates in plasma-assisted processes.
Semiconductor device density on chips has dramatically increased since such chips were first introduced several decades ago. One way to increase device density on a chip is to decrease the area per device. Typically, as device area decreases,
the aspect ratios, i.e., the height relative to the width, of features on the device often increase. This is particularly true for metallization traces that maintain a cross-sectional area sufficient to carry the current required for device operation.
Additionally, as device area decreases, the spacing between device features gets smaller. Today's devices often have geometries with less than 1 .mu.m spacing between features. These effects combine to form closely spaced, high-aspect-ratio
gaps that benefit from being filled with dielectric material.
Narrow, high-aspect-ratio gaps are difficult to fill in prior art CVD processes because the CVD material, accumulating on the corners of adjacent features as overhangs, often closes the gap from both sides before the gap is filled. FIG. 1A shows
a vertical cross-sectional view of a partially processed substrate. The substrate has a conductive layer 115. This layer was previously deposited on substrate 100. Substrate 100 may be a wafer, specifically a semiconductor wafer, and more
specifically, a silicon wafer. A first portion of a dielectric layer 130 has been deposited over the substrate. As shown, dielectric material has accumulated at the edges 135 to form overhangs 140.
FIG. 1B shows a vertical cross-sectional view of a substrate upon completion of the deposition of layer 150. Overhangs 140 have grown together, leaving an interior gap 145. This gap can cause problems relating to device fabrication, operation,
and reliability. Various methods have been employed in an attempt to avoid forming this gap. One method is to deposit a partial layer of CVD dielectric, then to spin on a layer of low-melting-point glass that is subsequently heated so that it flows
into and fills the gap. Other methods use sequential or concurrent deposition and sputtering to keep the gaps open until they are filled. Using a simultaneous deposition and etching process may also keep the gaps open until they are filled.
Because fluorine (F) is an etching species, fluorine simultaneously etches the layer as it is being deposited, and helps to keep the gaps open until they are filled. The simultaneous deposition and etching allows fluorine-doped silicon oxide
films to have improved gap filling capabilities, such that the films are able to adequately fill gaps having an aspect ratio of between 1.8 to 4, or more, between adjacent metal layers. As is well known to those skilled in the art, fluorine-doped
silicon oxide films are basically silicon dioxide modified with fluorine, and may vary in the local or the overall stoichiometric ratio of silicon to oxygen, and may be in an amorphous phase or a crystalline phase, or combinations thereof.
Another problem associated with higher device densities relates to the parasitic capacitive effects between conductive layers. Reducing the spacing between conductive layers often has the effect of bringing the plates of a capacitor closer
together. This increases unwanted capacitance, resulting in several undesirable effects. For example, the resistive-capacitive (RC) time constant of a conductive trace may increase, requiring greater power for the same speed of operation of the
circuit, or conductive layers may capacitively couple, resulting in "crosstalk." Lowering the dielectric constant of insulating layers between conductive layers would reduce these undesired effects by reducing the capacitance.
Many approaches to obtain lower dielectric constants have been proposed. One of the more promising solutions is the incorporation of fluorine or other halogen elements, such as chlorine or bromine, into a silicon oxide (S.sub.i O.sub.x) layer.
Examples of halogen incorporation in films are described in U.S. patent application Ser. Nos. 08/548,391, filed Oct. 25, 1995 and entitled "METHOD AND APPARATUS FOR IMPROVING FILM STABILITY OF HALOGEN-DOPED SILICON OXIDE FILMS", 08/538,696, filed
Oct. 2, 1995 and entitled "USE OF SIF.sub.4 TO DEPOSIT F-DOPED FILMS OF GREATER STABILITY", which are assigned to Applied Materials, Inc.
It is believed that fluorine, the preferred halogen dopant for silicon oxide films, lowers the dielectric constant of the silicon oxide film because fluorine is an electronegative atom that decreases the polarizability of the overall SiO-F
network. Fluorinated silicon oxide films are also referred to as fluorinated silicon glass (FSG) films. Unfortunately, FSG layers may take a relatively long time to deposit.
FIG. 2 shows that increasing the relative concentration of silicon tetrafluoride silane (SiF.sub.4) to (SiH.sub.4) increases the time required to deposit a given thickness of dielectric, and that the rate of deposition decreases with increasing
time or layer thickness. It is believed that this occurs because the plasma heats the surface of the layer as it grows. Fluorine acts as an etchant of the layer, and etching is more pronounced at higher temperatures and at higher fluorine
concentrations.
Another factor affecting the deposition rate of the layer is that the layer may dissociate back into the plasma more rapidly at higher temperatures. This dissociation is in addition to any plasma etching and fluorine etching that may occur.
However, it is believed that more fluorine is incorporated into the growing layer at higher temperatures. Fluorine that is not incorporated, or is loosely incorporated, into the layer may remain as free fluorine. Free fluorine may absorb water,
increasing the dielectric constant of the layer, and may form hydrofluoric acid, which can attack metal and oxide layers on the layer.
Incorporated fluorine reduces the dielectric constant of the layer, which is a desirable characteristic. However, the higher temperatures that increase fluorine incorporation also increase the etch rate and dissociation of the layer. Therefore,
the desired temperature for greatest fluorine incorporation may result in an unattractively slow deposition rate.
FIG. 3 shows that the dielectric constant of a continuously deposited, fluorine-doped layer decreases with thickness. Therefore, a layer 401 deposited in a single step may have a graded dielectric constant, as shown in FIG. 4. Although the
entire layer is shown as a sum of four sublayers, this is a representation. It is likely that the dielectric constant decreases in a monotonic fashion from an initial high value to a final low value. It is believed that this is due to the surface
temperature of the layer increasing with time, which increases the fluorine concentration in the layer and reduces the dielectric constant.
Thus, manufacturers desire to include fluorine in various dielectric layers, and particularly in intermetal dielectric layers, to lower the dielectric constant. It is also desired that these layers be deposited in the least amount of time, and
that the dielectric constant be fairly uniform across the layer. It is further desired that these layers fill gaps between features less than 0.5 .mu.m apart with an aspect ratio greater than 1.8.
SUMMARY OF THE INVENTION
The present invention solves the problems described above by providing an efficient process for depositing a layer of halogen-doped silicon dioxide, with a nearly uniform dielectric constant less than 4, in high-aspect-ratio trenches on a
substrate. The material is deposited from chemical vapor, preferably in a high-density plasma-chemical vapor deposition (HDP-CVD) system, such as an Applied Materials, Inc. Ultima System.
A high-aspect-ratio trench may be formed from prior processing steps, such as aluminum deposition and patterning steps on a silicon wafer, the trench being at least about 1.8 times higher than it is wide. The gap in such a trench may be narrow,
such as from about 0.5 to 0.18 .mu.m, or less. In order to fill the trench without leaving voids, an HDP-CVD system uses deposition gases, such as SiH.sub.4 and oxygen, halogen-containing gas, such as SiF.sub.4, and a sputtering gas, such as argon, in a
plasma-assisted deposition process. The HDP-CVD system has an RF source power supply and an RF bias power supply that provide the RF energy delivered to the plasma. The combination of source RF energy and bias RF energy helps to prevent damage to
pre-existing features on the substrate while providing a high density plasma.
As the layer is deposited, it is concurrently etched. Etching arises from both nonreactive (also known as sputter-etching), and reactive (etchant), plasma species. The RF bias power applied to the plasma is reduced during the process to reduce
the surface temperature of the substrate during layer formation, which reduces the reactivity of the etchant species, and to reduce the sputtering component of the plasma. Reducing the surface temperature of the substrate increases the net deposition
rate under some process conditions. This provides efficient gap-filling characteristics by keeping high-aspect-ratio trenches open while they fill in. This process results in a low-dielectric-constant, halogen-doped silicon dioxide layer at a higher
rate of deposition than present processes allow.
In one embodiment, the RF bias power is reduced during the deposition process to reduce the surface temperature of the substrate and hence increase the rate of deposition relative to the rate of etching. The bias power is maintained at a level
sufficient to promote rapid growth of the deposited layer under the conditions present in the deposition system. In this embodiment, the flow of deposition and etchant gases may be increased to further increase the net deposition rate.
In another embodiment, a process gas comprising at least a silicon source, an oxygen source, and a fluorine source is introduced into a reaction chamber to deposit a FSG film. The process gas may also comprise a nonreactive sputtering gas, such
as argon. The initial ratio of fluorine to silicon is high enough to ensure that the first portion of the FSG film has a low dielectric constant, and to ensure a proper deposition-to-etch ratio so that the gaps between device features remain open while
the trench is filled. The concentration of the etchant-containing gas relative to the deposition gas is reduced during the deposition of the layer to increase the deposition-to-etch ratio and insure that the layer is deposited in a timely manner.
The deposition to etch ratio is a combination of many factors. The plasma has a source component, which dissociates the atoms and molecules of the chamber gases into a plasma, and a bias component, which moves the plasma species to and from the
surface of the forming layer. The bias component conveys deposition ions to the layer surface for combination into the layer material, knocks loose layer material via sputtering, and conveys etchant ions to the surface, removing some layer material by
etching.
The deposition-to-etch ratio may be increased by either increasing the deposition rate at a substantially constant etch rate, or by decreasing the etch rate at a substantially constant deposition rate. Decreasing the RF bias energy increases the
deposition-to-etch ratio because it both decreases the etch rate by decreasing the activity of the etchant species, and increases the deposition rate by reducing the surface temperature of the substrate, which increases the rate of growth of the layer.
For a further understanding of the objects and advantages of the present invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a vertical cross-sectional view of a partially processed prior-art substrate, showing the accumulation of deposit on the edges of the features defining high-aspect-ratio trenches.
FIG. 1B is a vertical cross-sectional view of the prior-art substrate of FIG. 1A, showing the voids formed in the high-aspect-ratio trenches on completion of the deposition process.
FIG. 2 is a graph representing the rate of growth of an FSG layer for various ratios of SiF.sub.4 :SiH.sub.4.
FIG. 3 is a graph showing the decrease in dielectric constant versus film thickness of an FSG layer grown at a constant SiF.sub.4 :SiH.sub.4 ratio of 0.5.
FIG. 4 is a vertical cross-sectional view of the prior-art FSG layer when deposited with a constant SiF.sub.4 :SiH.sub.4 ratio of nominally 0.5, showing a variation in the relative dielectric constant.
FIG. 5A is a simplified diagram of one embodiment of a HDP-CVD system according to the present invention.
FIG. 5B is a simplified cross section of a gas ring that may be used in conjunction with the exemplary CVD processing chamber of FIG. 5A.
FIG. 5C is a simplified diagram of a monitor and light pen that may be used in conjunction with the exemplary CVD processing chamber of FIG. 5A.
FIG. 5D is a flow chart of an exemplary process control computer program product used to control the exemplary CVD processing chamber of FIG. 5A.
FIG. 6 is a simplified cross-sectional view of an integrated circuit according to the present invention.
FIGS. 7A, 7B, and 7C are simplified cross-sectional views of an insulating film being deposited in a gap, according to the present invention.
FIG. 8 is a simplified cross-sectional view of an insulating film deposited according to the present invention.
FIG. 9 is a flow chart illustrating the steps performed in applying an insulating film using a process according to the process of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
I. Introduction
In one embodiment, a halogen-doped layer of silicon dioxide having a dielectric constant less than undoped silicon glass is deposited in a standard HDP-CVD system. A high deposition rate is achieved by varying the etching effect of the fluorine
while the layer is deposited. The resulting layer has a more uniform dielectric constant and less free fluorine than similar layers grown by other methods.
II. An Exemplary CVD System
FIG. 5A illustrates one embodiment of a HDP-CVD system 10, in which a dielectric layer according to the present invention can be deposited. System 10 includes a chamber 13, a vacuum system 70, a source plasma system 80A, a bias plasma system
80B, a gas delivery system 33, and a remote plasma cleaning system 50.
The upper portion of chamber 13 includes a dome 14, which is made of a dielectric material, such as alumina or aluminum nitride. Dome 14 defines an upper boundary of a plasma processing region 16. Plasma processing region 16 is bounded on the
bottom by the upper surface of substrate 17 and the substrate support member 18.
A heater plate 23 and a cold plate 24 surmount, and are thermally coupled to, dome 14. Heater plate 23 and cold plate 24 allow control of the dome temperature to within about .+-.10.degree. C. over a range of about 100.degree. C. to
200.degree. C. This allows optimizing the dome temperature for the various processes. For example, it may be desirable to maintain the dome at a higher temperature for cleaning or etching processes than for deposition processes. Accurate control of
the dome temperature also reduces the flake or particle counts in the chamber and improves adhesion between the deposited layer and the substrate.
The lower portion of chamber 13 includes a body member 22, which joins the chamber to the vacuum system. A base portion 21 of substrate support member 18 is mounted on, and forms a continuous inner surface with, body member 22. Substrates are
transferred into and out of chamber 13 by a robot blade (not shown) through an insertion/removal opening (not shown) in the side of chamber 13. A motor (not shown) raises and lowers a lift-pin plate (not shown) that raises and lowers lift pins (not
shown) that raise and lower the wafer. Upon transfer into chamber 13, substrates are loaded onto the raised lift pins, and then lowered to a substrate receiving portion 19 of substrate support member 18. Substrate receiving portion 19 includes an
electrostatic chuck 20 that secures the substrate to substrate support member 18 during substrate processing.
Vacuum system 70 includes throttle body 25, which houses twin-blade throttle valve 26 and is attached to gate valve 27 and turbomolecular pump 28. It should be noted that throttle body 25 offers minimum obstruction to gas flow, and allows
symmetric pumping, as described in co-pending, co-assigned United States Patent Application, originally filed on filed Dec. 12, 1995, and assigned Ser. No. 08/574,839, refiled on Sep. 11, 1996 and assigned Ser. No. 08/712724 entitled "SYMMETRIC
CHAMBER". Gate valve 27 can isolate pump 28 from throttle body 25, and can also control chamber pressure by restricting the exhaust flow capacity when throttle valve 26 is fully open. The arrangement of the throttle valves, gate valve, and
turbomolecular pump allow accurate and stable control of chamber pressures from about 1 to 100 millitorr.
The source plasma system 80A includes a top coil 29 and side coil 30, mounted on dome 14. A symmetrical ground shield (not shown) reduces electrical coupling between the coils. Top coil 29 is powered by top source RF generator 31A, while side
coil 30 is powered by side source RF generator 31B, allowing independent power levels and frequencies of operation for each coil. This dual coil system allows control of the radial ion density in chamber 13, thereby improving plasma uniformity. Side
coil 30 and top coil 29 are typically inductively driven, which does not require a complementary electrode. In a specific embodiment, the top source RF generator 31A provides up to 2500 W of RF power at nominally 2 MHz and the side source RF generator
31B provides up to 5000 W of RF power at nominally 2 MHz. The operating frequencies of the top and side RF generators may be offset from the nominal operating frequency (e.g., to 1.7-1.9 MHz and 1.9-2.1 MHz, respectively) to improve plasma-generation
efficiency.
A bias plasma system 80B includes a bias RF generator 31C and a bias matching network 32C. The bias plasma system 80B capacitively couples substrate receiving portion 19 to body member 22, which act as complementary electrodes. The bias plasma
system 80B serves to enhance the transport of plasma species created by the source plasma system 80A to the surface of the substrate. In a specific embodiment, bias RF | | |
