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| United States Patent | 6137570 |
| Link to this page | http://www.wikipatents.com/6137570.html |
| Inventor(s) | Chuang; Yung-Ho (Cupertino, CA); Armstrong; J. Joseph (Milpitas, CA); Brown; David L. (Sunnyvale, CA); Lin; Jason Z. (Saratoga, CA); Tsai; Bin-Ming Benjamin (Saratoga, CA) |
| Abstract | Disclosed is a method and apparatus for using far field scattered and
diffracted light to determine whether a collection of topological features
on a surface (e.g., a semiconductor wafer) conforms to an expected
condition or quality. This determination is made by comparing the far
field diffraction pattern of a surface under consideration with a
corresponding diffraction pattern (a "baseline"). If the baseline
diffraction pattern and far field diffraction pattern varies by more than
a prescribed amount or in characteristic ways, it is inferred that the
surface features are defective. The method may be implemented as a
die-to-die comparison of far field diffraction patterns of two dies on a
semiconductor wafer. The portion of the far field scattered and diffracted
light sensitive to a relevant condition or quality can also be reimaged to
obtain an improved signal-to-noise ratio. |
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Title Information  |
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Drawing from US Patent 6137570 |
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System and method for analyzing topological features on a surface |
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| Publication Date |
October 24, 2000 |
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| Filing Date |
June 30, 1998 |
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Title Information  |
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| | Reference | Relevancy | Comments | Reference | Relevancy | Comments | 5825043 Suwa 250/548 Oct,1998 |      Your vote accepted [0 after 0 votes] | | 5659390 Danko 356/237.4 Aug,1997 |      Your vote accepted [0 after 0 votes] | | 5619429 Aloni 700/279 Apr,1997 |      Your vote accepted [0 after 0 votes] | | 5578821 Meisberger 250/310 Nov,1996 |      Your vote accepted [0 after 0 votes] | | 5572598 Wihl 382/144 Nov,1996 |      Your vote accepted [0 after 0 votes] | | 5563702 Emery 356/73 Oct,1996 |      Your vote accepted [0 after 0 votes] | | 5546181 Kobayashi
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Market Review  |
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Technical Review  |
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Claims  |
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What is claimed is:
1. A method for analyzing the condition of a surface of an electronic device, the surface having a defined pattern, the method comprising:
(a) illuminating a first region of the surface such that light is scattered and diffracted off of features of the surface;
(b) detecting light scattered and diffracted from the first region surface;
(c) comparing the diffracted light detected to a baseline diffraction
pattern of light diffracted from a baseline region having a condition corresponding to an expected condition of the first region; and
(d) determining whether the detected light diffracted from the first region significantly deviates from the baseline diffraction pattern.
2. The method of claim 1, wherein the light diffracted from the first region of the surface forms a far field diffraction pattern that is detected.
3. The method of claim 1, wherein the light diffracted from the first region of the surface forms a far field diffraction pattern of which only a single point of light is imaged.
4. The method of claim 1, wherein the illuminating is performed using a monochromatic coherent light source.
5. The method of claim 4, wherein the monochromatic coherent light source is a laser.
6. The method of claim 1, wherein the surface is a semiconductor wafer surface, the first region is a first die or zone on the semiconductor wafer, and the second region is a second die or zone on the semiconductor wafer.
7. The method of claim 1, wherein the baseline diffraction pattern is diffraction data taken from a surface having the expected condition of the first region.
8. The method of claim 1, further comprising selecting the baseline image from a database of images, the database of images comprising diffraction patterns of regions which vary from a nominal image for the first region.
9. The method of claim 1, further comprising:
filtering or polarizing far field light before detecting light diffracted from the first region of the surface.
10. A method for inspecting a plurality of openings in a film on a substrate, comprising:
illuminating a first portion of said openings;
detecting far field diffracted light produced by said illumination of said first portion;
illuminating a second portion of said openings, said second portion of said openings having a pattern which is substantially identical to said first portion;
detecting far field diffracted light produced by said illumination of said second portion; and
comparing signals detected from illumination of said first portion with signals detected from illumination of said second portion, thereby determining whether variations exist in said openings.
11. The method of claim 10, wherein the film is a dielectric layer on a semiconductor wafer.
12. The method of claim 11, wherein the openings are vias or contact holes in the dielectric layer.
13. The method of claim 10, wherein the first portion is a first die on a semiconductor wafer and wherein the second portion is a second die on the semiconductor wafer.
14. The method of claim 10, wherein detecting far field diffracted light produced by the illumination of the first portion or the second portion comprises detecting the diffracted light proximate a Fourier plane.
15. The method of claim 10, wherein detecting far field diffracted light produced by the illumination of the first portion or the second portion comprises detecting multiple orders of diffracted illumination.
16. An apparatus for evaluating the condition of topological features on a substrate surface, the apparatus comprising:
a light source arranged to direct light onto the substrate surface such that the light is diffracted by the substrate surface;
a sensor configured to capture and transmit a diffraction pattern of the light diffracted by the substrate surface; and
a computer configured to compare the diffraction pattern from the substrate surface with a baseline diffraction pattern of light diffracted from a baseline surface having a condition corresponding to an expected condition of the substrate
surface.
17. The apparatus of claim 16, further comprising optics aligned to capture light diffracted from the substrate surface and direct it onto the sensor.
18. The apparatus of claim 16, further comprising:
a memory device for storing the baseline diffraction pattern, the memory device being coupled to the computer or being a component of the computer.
19. The apparatus of claim 18, wherein the memory device is a database storing a plurality of baseline diffraction patterns for multiple expected conditions of the substrate surface.
20. The apparatus of claim 16, wherein the light source is a coherent light source.
21. The apparatus of claim 20, wherein the light source is a laser.
22. The apparatus of claim 16, wherein the sensor is a camera.
23. The apparatus of claim 16, wherein the sensor is a charge coupled device or a photodiode array.
24. The apparatus of claim 1, further comprising a Fourier filter oriented to block one or more regions of the diffraction pattern from the substrate surface.
25. The apparatus of claim 1, further comprising optics comprising a microscope for providing views of the substrate surface.
26. The apparatus of claim 1, wherein the apparatus is configured to image only a portion of the diffracted light, which portion is sensitive to a particular surface condition.
27. A method for analyzing the condition of a surface of an electronic device, the surface having a defined pattern, the method comprising:
(a) illuminating a first region of the surface such that light is diffracted off of features the surface;
(b) filtering diffracted light to block one or more portions of a diffraction pattern from the substrate surface which portions contain little or no information pertaining to a surface feature of interest, while passing diffracted light
containing information relevant to the surface feature of interest;
(c) detecting the filtered diffracted light; and
(d) comparing the filtered diffracted light to a baseline diffraction pattern of light diffracted from a baseline region having a condition corresponding to an expected condition of the surface feature of interest.
28. The method of claim 27, further comprising:
(e) determining whether the detected light diffracted from the first region significantly deviates from the baseline diffraction pattern.
29. The method of claim 27, wherein the filtered diffracted light produces a spatial image which is detected. |
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Claims  |
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Description  |
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BACKGROUND OF THE INVENTION
This invention relates to a method and apparatus for evaluating surface features such as those on a partially fabricated integrated circuit. More specifically, the invention relates to methods and apparatus for using the far-field pattern of
scattered and diffracted light from the surface features to evaluate the quality or condition of the features.
Many optical and electronic systems exist for identifying and classifying surface feature errors such as those on a partially fabricated integrated circuit or a reticle. These errors may take the form of particles randomly localized on the
surface, scratches, process variations such as under etching, etc. Such techniques and apparatus are well known in the art and are embodied in various commercial products such as many of those available from KLA-Tencor Corporation of San Jose, Calif.
Relatively few techniques are available for evaluating the condition of surface features (e.g., contacts, vias, deep trenches, polysilicon gate structures, reticle features, etc.). Most generally, these surface features may be viewed as design
features which show up as topological variations on a surface. Often, one wishes to know whether or not such features (as formed in a conventional process) fall within specified tolerances. For example, the depth, diameter and slope of a contact hole
or via should fall within specified tolerances. If a contact hole is etched too deeply, it may cut into the substrate and thereby detrimentally effect the electrical performance of a transistor. An over etched via may cut through an underlying contact
to change resistance, etc. If a via is under etched (not sufficiently deep), there may be no contact between an upper level metallization line and a lower level metallization. If a via is etched too narrowly, the current density in the resulting
interconnect may be too high, possibly resulting in premature failure.
These and similar problems often arise when processing equipment malfunctions or degrades in performance over time. Examples of such equipment include plasma etchers, deposition systems, chemical mechanical planarization systems, reticle
processing, and photolithography equipment. Obviously, a manufacturer needs to know when the process equipment ceases to function in an acceptable manner.
A few techniques do exist for evaluating the condition of topologic features on a reticle or integrated circuit. The simplest of these involves a casual visual inspection by a technician of a wafer held in white light and examined to determine
whether there is any variation in the appearance of the various dies fabricated on the wafer. Ideally, each die should have the same appearance when moved about under a white light. If there is any variation in the appearance of one or more of the dies
on the wafer, then it can be assumed the dies are not structurally identical and some problem exists. A related technique simply involves performing optical microscopy (e.g., bright field or dark field imaging) on the various dies of a wafer. Any
variation in the image of the individual die indicates that there is a problem in at least that die. However, due to the trend of small design rule, high aspect ratio, and the complexity of the background circuit, defective vias or contact holes are at
times difficult to detect through standard microscopic methods.
More accurate techniques exist for evaluating surface features. For example, ion milling may be employed to evaluate the condition of a section of an integrated circuit. Ion milling cuts through the circuit creating a cross section at a
location of interest, possibly an area where vias are suspected of being defective. Subsequently, a scanning electron micrograph images the cross section. From this, over etching, under etching, defective profiles, etc. in the vias can be visualized.
Unfortunately, this technique destroys the integrated circuit.
In some cases, scanning electron microscopy or a similar electron beam technique is employed to image the surface of a die (as opposed to a cross section). While this technique does not necessarily destroy the integrated circuit, the electrons
may damage the substrate surface. Further, both ion milling and scanning electron microscopy are currently very slow processes and therefore unsuitable for regular use in the normal process flow of an integrated circuit fabrication facility.
What is needed therefore is a rapid, non-destructive, and inexpensive technique for evaluating non-random topological variations on the surface of a substrate such as a partially fabricated integrated circuit or a reticle.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus of using far-field scattered and diffracted light to determine whether a collection of topological features on a surface (e.g., a semiconductor wafer) conforms to an expected condition or
quality. This determination can be made by comparing the far-field pattern (preferably at or near the Fourier plane) of a surface under consideration with a corresponding far-field pattern (a "baseline"). If the far-field patterns vary by more than a
prescribed amount, it is assumed that some aspect of the surface features is defective. In one embodiment, this invention is implemented using a die-to-die comparison of far-field patterns of two or more dies on a semiconductor wafer. The portion of
the far-field scattered and diffracted light sensitive to a relevant condition or quality (e.g., etch depth) can also be imaged to obtain an improved signal-to-noise ratio for detecting the condition of interest over so called nuisance defects which do
not impact the fabrication process.
One aspect of the present invention provides a method for determining the condition or changes in the condition of surface features defining a pattern on an electronic device. The method may be characterized as including the following sequence:
(a) illuminating a region of the surface such that light is scattered and diffracted off surface features; (b) detecting the scattered and diffracted light from the surface features; (c) comparing the far-field pattern of scattered and diffracted light
to baseline information; and (d) determining whether the far-field pattern from the first region significantly deviates from the baseline information. Often the method will benefit from selecting the polarization of the illuminating light. Also, the
method will often benefit from optically filtering or analyzing the scattered and diffracted light from the features on the surface before detecting the light.
The baseline information may be obtained from a variety of sources. For example, it may be calculated according to a method which predicts a pattern of scattered and diffracted light. Alternatively, it may be measured far-field data taken from
light scattered and diffracted off a surface having a known condition. In some instances, the baseline information may be selected from a database which stores a collection of far-field patterns (e.g., patterns for a nominal surface and a plurality of
surfaces with vary from a nominal image for the first region).
The scattered and diffracted light that is detected may be any portion of the far-field pattern. In some cases, it will include multiple diffraction orders or regions. In other cases, it will include only one or a few diffraction orders or
regions. This depends on what information is required and how much of that information is contained in one or a small group of diffraction orders or particular regions. If a manufacturer is concerned only with changes in the depth of its vias, it may
detect only those diffraction orders or regions that vary significantly with depth changes. By limiting detection to only those diffraction orders or regions that contain important information, the signal-to-noise ratio and speed of the method improves.
Another aspect of the invention provides a method for inspecting a single or plurality of openings in a film on a substrate. The method may be characterized as including: (a) illuminating a first portion of the openings; (b) detecting the
far-field scattered and diffracted light; (c) illuminating a second portion of the openings, the second portion of the openings having a pattern which is substantially identical to the first portion; (d) detecting far-field scattered and diffracted light
produced by the illumination of the second portion; and (e) comparing signals detected from illumination of the first portion with signals detected from illumination of the second portion, thereby determining whether variations exist in the openings.
In one embodiment, the surface is a dielectric layer on a semiconductor wafer and the openings are contact holes or vias in the dielectric layer. In the case of a die-to-die comparison, the first portion is a region of a first die on a
semiconductor wafer and the second portion is a region located at the same relative position of a second die on the semiconductor wafer. In the case of die-to-database comparison, the first portion is a die on a semiconductor wafer and the second
portion is a stored representation for that location.
Yet another aspect of the invention provides an apparatus for evaluating the condition of topological features on a substrate surface. In this aspect, the apparatus may be characterized as including the following features: (a) a light source
arranged to direct light onto the substrate surface such that the light is scattered and diffracted by the substrate surface; (b) a sensor configured to capture and detect a diffraction pattern of the light scattered and diffracted by the substrate
surface; and (c) a computer configured to compare the diffraction pattern from the substrate surface with a baseline diffraction pattern of light scattered
and diffracted from a baseline surface having a condition corresponding to an expected condition of the substrate surface. Often the apparatus will also require optics aligned to capture light scattered and diffracted from the substrate surface
and direct it onto the sensor.
Preferably, the light source is a coherent light source such as a laser. The sensor may be a camera or other detector such as a charge coupled device, CMOS photodiode array, or a single element detector.
The apparatus may include optics to capture light scattered and diffracted from the substrate surface and direct it onto the sensor. In a preferred embodiment, the optics are capable of capturing diffraction angles from normal to near 85
degrees. The optics can also support illumination of the substrate surface at the desired angles. The optics may also be configured to produce a pupil plane that can support Fourier filtering. A Fourier filter or aperture can be used to block or
attenuate one or more regions of the diffraction pattern from the substrate surface. The design and orientation of the Fourier filter or aperture allows portions of the diffraction pattern relevant to the problem at hand to pass to the sensor while
blocking or attenuating other less relevant portions of the diffraction pattern thereby improving signal-to-noise ratio for detecting changes critical to device fabrication. The apparatus may optionally include other optical elements such as optics
comprising a microscope for providing spatial imaging of the substrate surface.
In a preferred embodiment, the apparatus also includes a memory device coupled to the computer or being a component of the computer. The memory device will store at least one baseline diffraction pattern. In a particularly preferred embodiment,
the memory device is a database storing a plurality of baseline diffraction patterns for multiple expected conditions of the substrate surface and for different locations on the surface.
The features and advantages of this invention may be
further appreciated with reference to the following detailed description and associated drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1a is a laser diffraction order energy distribution for a properly formed via array.
FIG. 1b is a laser diffraction order energy distribution taken under the same conditions used to generate the distribution of FIG. 1a, but for clogged vias.
FIG. 2 is a graph showing variations in total collected energy for an entire diffraction pattern and high-order collected energy for the diffraction pattern for similar contact arrays with differing diameter and contact etch times.
FIG. 3 is a simplified hypothetical illustration of a die-to-die comparison of scattered and diffracted illumination in accordance with an embodiment of this invention.
FIG. 4 is a schematic illustration of various components in an apparatus for detecting and comparing diffraction signals in accordance with one embodiment of this invention.
FIG. 5 is a schematic illustration of various components in an apparatus for detecting and comparing diffraction signals in accordance with another embodiment of this invention.
FIG. 6 is an embodiment of an optical system that can support illumination of the substrate surface and capturing the scattered and diffracted light at angles up to 79 degrees.
FIG. 7 is an embodiment of an optical system that can collect the far-field light and form an image of the surface features.
FIG. 8 is a high level process flow diagram of a method that may be used to implement the present invention.
FIG. 9 is a process flow diagram of a method for comparing a baseline diffraction pattern with a recently acquired diffraction pattern in accordance with an embodiment of the present invention.
FIG. 10a is a computer simulation of a far-field pattern produced by good vias.
FIG. 10b shows the sensitivity of the diffracted orders in FIG. 10a to a particular process error.
FIG. 11 is a high level process flow diagram of a method that may be used to characterize errors in surface features.
FIG. 12a is the result of die-to-die comparisons of a die with known good vias and dies on a wafer with good vias.
FIG. 12b is the result of die-to-die comparisons of a die with known good vias and dies on a wafer with bad vias in the center dies.
FIG. 13 is a diagram that shows a hypothetical process history that could b | | |