Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines

Claims

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. A memory device comprising:

a first pair of data path circuits, wherein each of the data path circuits comprises a data write circuit, a data read circuit and a section select circuit, arranged adjacent to each other in a first direction; and

at least one block of memory cells connected to each data path circuit of said first pair of data path circuits and arranged in said first direction with respect to said first pair of data path circuits such that said first pair of data path circuits is located between said block of memory cells, said memory cells of each of said blocks being organized into an array having rows and columns.

2. The memory device of claim 1 wherein each of said data path circuits is associated with and positioned adjacent to two of said blocks of memory in said first direction, both of said blocks of memory being on a same side of an associated data path circuit.

3. The memory device of claim 2 wherein each of said data path circuits are associated with at least another two of said blocks of memory in a second direction.

4. The memory device of claim 1 wherein each of said data path circuits is associated with and positioned adjacent to four of said blocks of memory in said first direction, all four of said blocks of memory being on a same side of an associated data path circuit.

5. The memory device of claim 4 wherein each of said data path circuits are associated with at least another four of said blocks of memory in a second direction.

6. The memory device of claim 1 further comprising:

at least a second pair of data path circuits arranged adjacent to each other in said first direction; and

at least one block of memory cells connected to each of said second pair of data path circuits in said first direction, each of said block of memory cells comprising:

a plurality of word lines, each of said word lines being respectively connected to a row of memory cells of said block;

a plurality of digit lines, each of said digit lines being respectively connected to a column of memory cells of said block;

at least one row decoder, each of said row decoders connected to said word lines of said block; and

a plurality of sense amplifier circuits for reading data from and writing data to said memory cells, said sense amplifier circuits being respectively connected to said digit lines of said block, said sense amplifier circuits having a plurality of data transferring lines for transferring data between a respective one of said data path circuits and said sense amplifier circuits;

said second pair of data path circuits and their associated blocks of memory cells being arranged in a second direction orthogonal to said first direction with respect to said first pair of data path circuits and their associated blocks of memory cells.

7. The memory device of claim 6 further comprising a selection circuit for selectively coupling sense amplifier circuits from adjacent blocks of memory arranged in said second direction to a data path circuit associated with one of said adjacent blocks, said associated data path circuits reading data from or writing data to a selected one of said adjacent blocks.

8. The memory device of claim 7 wherein each data path circuit comprises:

a plurality of write driver circuits connectable to said sense amplifier circuits, each of said write driver circuits having a data write line for inputting data into said sense amplifier circuits; and

a plurality of read driver circuits connectable to said sense amplifier circuits, each of said read driver circuits having a data read line for outputting data from said sense amplifier circuits.

9. The memory device of claim 7 wherein each block of memory cells includes two row decoders located on opposite sides of said block, said row decoders respectively activating alternate word lines within a block.

10. The memory device of claim 1 wherein each of said blocks of memory comprise at least 64K memory cells.

11. The memory device of claim 1 wherein each of said blocks of memory comprise at least 128K memory cells.

12. The memory device of claim 1 wherein each of said blocks of memory comprise at least 256K memory cells.

13. The memory device of claim 1 wherein each of said blocks of memory comprise at least 512K memory cells.

14. The memory device of claim 1 wherein each of said blocks of memory comprise at least 1024K memory cells.

15. A memory circuit comprising:

at least one memory module residing on a semiconductor device, each of said memory modules comprising:

a first pair of data path circuits, wherein each of the data path circuits comprises a data write circuit, a data read circuit and a section select circuit, arranged adjacent to each other in a first direction; and

at least one block of memory cells connected to each data path circuit of said first pair of data path circuits and arranged in said first direction with respect to said first pair of data path circuits such that said first pair of data path circuits is located between said block of memory cells, said memory cells of each of said blocks being organized into an array having rows and columns; and

a column decoder, said column decoder connected to sense amplifier circuitry of said memory module.

16. The memory circuit of claim 15 wherein each of said data path circuits is associated with and positioned adjacent to two of said blocks of memory in said first direction, both of said blocks of memory being on a same side of an associated data path circuit.

17. The memory circuit of claim 16 wherein each of said data path circuits are associated with at least another two of said blocks of memory in a second direction.

18. The memory circuit of claim 15 wherein each of said data path circuits is associated with and positioned adjacent to four of said blocks of memory in said first direction, all four of said blocks of memory being on a same side of an associated data path circuit.

19. The memory circuit of claim 18 wherein each of said data path circuits are associated with at least another four of said blocks of memory in a second direction.

20. The memory circuit of claim 15 wherein said memory modules further comprise:

at least a second pair of data path circuits arranged adjacent to each other in said first direction; and

at least one block of memory cells connected to each of said second pair of data path circuits in said first direction, each of said block of memory cells comprising:

a plurality of word lines, each of said word lines being respectively connected to a row of memory cells of said block;

a plurality of digit lines, each of said digit lines being respectively connected to a column of memory cells of said block;

at least one row decoder, each of said row decoders connected to said word lines of said block; and

a plurality of sense amplifier circuits for reading data from and writing data to said memory cells, said sense amplifier circuits being respectively connected to said digit lines of said block, said sense amplifier circuits having a plurality of data transferring lines for transferring data between a respective one of said data path circuits and said sense amplifier circuits;

said second pair of data path circuits and their associated blocks of memory cells being arranged in a second direction orthogonal to said first direction with respect to said first pair of data path circuits and their associated blocks of memory cells.

21. The memory circuit of claim 20 wherein said memory module further comprises a selection circuit for selectively coupling sense amplifier circuits from adjacent blocks of memory arranged in said second direction to a data path circuit associated with one of said adjacent blocks, said associated data path circuits reading data from or writing data to a selected one of said adjacent blocks.

22. The memory circuit of claim 20 wherein each data path circuit comprises:

a plurality of write driver circuits connectable to said sense amplifier circuits, each of said write driver circuits having a data write line for inputting data into said sense amplifier circuits; and

a plurality of read driver circuits connectable to said sense amplifier circuits, each of said read driver circuits having a data read line for

outputting data from said sense amplifier circuits.

23. The memory circuit of claim 20 wherein each block of memory cells includes two row decoders located on opposite sides of said block, said row decoders respectively activating alternate word lines within said block.

24. The memory circuit of claim 15 wherein sense amplifier circuitry of at least two memory modules are connected to said column decoder and are positioned on the semiconductor device in a second direction orthogonal to a first direction.

25. The memory circuit of claim 15 wherein sense amplifier circuitry of at least four memory modules are connected to said column decoder and are positioned on the semiconductor device in a second direction orthogonal to a first direction.

26. The memory circuit of claim 25 wherein said at least four memory modules are configured into two columns in a first direction.

27. The memory circuit of claim 15 wherein sense amplifier circuitry of at least eight memory modules are connected to said column decoder and are positioned on the semiconductor device in a second direction orthogonal to a first direction.

28. The memory circuit of claim 27 wherein said at least eight memory modules are configured into two columns in a first direction.

29. The memory circuit of claim 15 wherein said memory circuit is an SGRAM memory circuit.

30. The memory circuit of claim 15 wherein said memory circuit is a DRAM memory circuit.

31. The memory circuit of claim 15 wherein said memory circuit is a RAM memory circuit.

32. The memory circuit of claim 15 wherein each of said blocks of memory comprise at least 64K memory cells.

33. The memory circuit of claim 15 wherein each of said blocks of memory comprise at least 128K memory cells.

34. The memory circuit of claim 15 wherein each of said blocks of memory comprise at least 256K memory cells.

35. The memory circuit of claim 15 wherein each of said blocks of memory comprise at least 512K memory cells.

36. The memory circuit of claim 15 wherein each of said blocks of memory comprise at least 1024K memory cells.

37. A computer system comprising:

a processor; and

a semiconductor device connected to said processor, said semiconductor device comprised of memory modules having sense amplifier circuitry connected to a column decoder, each of said memory modules comprising:

a first pair of data path circuits, wherein each of the data path circuits comprises a data write circuit, a data read circuit and a section select circuit, arranged adjacent to each other in a first direction; and

at least one block of memory cells connected to each data path circuit of said first pair of data path circuits and arranged in said first direction with respect to said first pair of data path circuits such that said first pair of data path circuits is located between said block of memory cells, said memory cells of each of said blocks being organized into an array having rows and columns.

38. The system of claim 37 wherein each of said data path circuits is associated with and positioned adjacent to two of said blocks of memory in said first direction, both of said blocks of memory being on a same side of an associated data path circuit.

39. The system of claim 38 wherein each of said data path circuits are associated with at least another two of said blocks of memory in a second direction.

40. The system of claim 37 wherein each of said data path circuits is associated with and positioned adjacent to four of said blocks of memory in said first direction, all four of said blocks of memory being on a same side of an associated data path circuit.

41. The system of claim 40 wherein each of said data path circuits are associated with at least another four of said blocks of memory in a second direction.

42. The system of claim 37 wherein said memory modules further comprise:

at least a second pair of data path circuits arranged adjacent to each other in said first direction; and

at least one block of memory cells connected to each of said second pair of data path circuits in said first direction, each of said block of memory cells comprising:

a plurality of word lines, each of said word lines being respectively connected to a row of memory cells of said block;

a plurality of digit lines, each of said digit lines being respectively connected to a column of memory cells of said block;

at least one row decoder, each of said row decoders connected to said word lines of said block; and

a plurality of sense amplifier circuits for reading data from and writing data to said memory cells, said sense amplifier circuits being respectively connected to said digit lines of said block, said sense amplifier circuits having a plurality of data transferring lines for transferring data between a respective one of said data path circuits and said sense amplifier circuits;

said second pair of data path circuits and their associated blocks of memory cells being arranged in a second direction orthogonal to said first direction with respect to said first pair of data path circuits and their associated blocks of memory cells.

43. The system of claim 42 wherein said memory module further comprises a selection circuit for selectively coupling sense amplifier circuits from adjacent blocks of memory arranged in said second direction to a data path circuit associated with one of said adjacent blocks, said associated data path circuits reading data from or writing data to a selected one of said adjacent blocks.

44. The system of claim 42 wherein each data path circuit comprises:

a plurality of write driver circuits connectable to said sense amplifier circuits, each of said write driver circuits having a data write line for inputting data into said sense amplifier circuits; and

a plurality of read driver circuits connectable to said sense amplifier circuits, each of said read driver circuits having a data read line for outputting data from said sense amplifier circuits.

45. The system of claim 42 wherein each block of memory cells includes two, row decoders located on opposite sides of said block, said row decoders respectively activating alternate word lines within said block.

46. The system of claim 37 wherein sense amplifier circuitry of at least two memory modules are connected to said column decoder and are positioned on the semiconductor device in a second direction orthogonal to a first direction.

47. The system of claim 37 wherein sense amplifier circuitry of at least four memory modules are connected to said column decoder and are positioned on the semiconductor device in a second direction orthogonal to a first direction.

48. The system of claim 47 wherein said at least four memory modules are configured into two columns in a first direction.

49. The system of claim 37 wherein sense amplifier circuitry of at least eight memory modules are connected to said column decoder and are positioned on the semiconductor device in a second direction orthogonal to a first direction.

50. The system of claim 49 wherein said at least eight memory modules are configured into two columns in a first direction.

51. The system of claim 37 wherein said semiconductor device is an SGRAM memory circuit.

52. The system of claim 37 wherein said semiconductor device is a DRAM memory circuit.

53. The system of claim 37 wherein said semiconductor device is a RAM memory circuit.

54. The system of claim 37 wherein each of said blocks of memory comprise at least 64K memory cells.

55. The system of claim 37 wherein each of said blocks of memory comprise at least 128K memory cells.

56. The system of claim 37 wherein each of said blocks of memory comprise at least 256K memory cells.

57. The system of claim 37 wherein each of said blocks of memory comprise at least 512K memory cells.

58. The system of claim 37 wherein each of said blocks of memory comprise at least 1024K memory cells.

59. A method of operating a memory circuit having at least a first and second array of memory cells and a first data path circuit, each of said arrays being connected to said first data path circuit, said method comprising:

activating one of a plurality of first word lines connected to a row of memory cells in said first array of memory cells associated with and connected to said first data path circuit;

activating a plurality of first digit lines connected to a column of memory cells in said first array having one of said first word lines activated;

transferring data between memory cells associated with and connected to said activated first word line and first digit line and said first data path circuit;

activating one of a plurality of second word lines connected to a row of memory cells in said second array associated with and connected to said first data path circuit;

activating a plurality of second digit lines connected to a column of memory cells in said second array having one of said second word lines activated;

transferring data between memory cells associated with and connected to said activated second word line and second digit line of said second array and said first data path circuit; and

wherein said transfer of data between memory cells of said first and second arrays and said first data path circuit is selectively performed by only one of said first and second arrays at a time.

60. The method according to claim 59 wherein said memory circuit contains a second data path circuit, said first and second arrays being connected to said second data path circuit, said method further comprises the steps of:

activating one of a plurality of first word lines connected to a row of memory cells in said first array of memory cells associated with and connected to said second data path circuit;

activating a plurality of first digit lines connected to a column of memory cells in said first array having one of said first word lines activated; and

transferring data between memory cells associated with and connected to said activated first word line and first digit line and said second data path circuit.

61. The method according to claim 59 wherein said memory circuit contains a second data path circuit, said first and second arrays being connected to said second data path circuit, said method further comprises the steps of:

activating one of a plurality of second word lines connected to a row of memory cells in said second array of memory cells associated with and connected to said second data path circuit;

activating a plurality of second digit lines connected to a column of memory cells in said second array having one of said second word lines activated; and

transferring data between memory cells associated with and connected to said activated second word line and second digit line and said second data path circuit.

62. A method of manufacturing a memory circuit comprising the steps of:

providing a first pair of data path circuits, wherein each of the data path circuits comprises a data write circuit, a data read circuit and a section select circuit, arranged adjacent to each other in a first direction;

providing al least one block of memory cells connected to each data path circuit of said first pair of data path circuits and arranged in said first direction with respect to said first pair of data path circuits such that said first pair of data path circuits is located between said block of memory cells, said memory cells of each of said blocks being organized into in array having rows and columns; and

providing a column decoder, connected to sense amplifier circuitry of said blocks of memory.

63. The method of claim 62 wherein each of said data path circuits is associated with and positioned adjacent to two of said blocks of memory in said first direction, both of said blocks of memory being on a same side of an associated data path circuit.

64. The method of claim 63 wherein each of said data path circuits are associated with at least another two of said blocks of memory in a second direction.

65. The method of claim 62 wherein each of said data path circuits is associated With and positioned adjacent to four of said blocks of memory in said first direction, all four of said blocks of memory being on a same side of an associated data path circuit.

66. The method of claim 65 wherein each of said data path circuits are

associated with at least another four of said blocks of memory in a second direction.

67. The method of claim 62 further comprising:

providing at least a second pair of data path circuits arranged adjacent to each other in said first direction; and

providing at least one block of memory cells connected to each of said second pair of data path circuits in said first direction, each of said block of memory cells comprising:

a plurality of word lines, each of said word lines being respectively connected to a row of memory cells of said block;

a plurality of digit lines, each of said digit lines being respectively connected to a column of memory cells of said block;

at least one row decoder, each of said row decoders connected to said word lines of said block; and

a plurality of sense amplifier circuits for reading data from and writing data to said memory cells, said sense amplifier circuits being respectively connected to said digit lines of said block, said sense amplifier circuits having a plurality of data transferring lines for transferring data between a respective one of said data path circuits and said sense amplifier circuits;

said second pair of data path circuits and their associated blocks of memory cells being arranged in a second direction orthogonal to said first direction with respect to said first pair of data path circuits and their associated blocks of memory cells.

68. The method of claim 67 wherein further comprising the step of providing a selection circuit for selectively coupling sense amplifier circuits from adjacent blocks of memory arranged in said second direction to a data path circuit associated with one of said adjacent blocks, said associated data path circuits reading data from or writing data to a selected one of said adjacent blocks.

69. The method of claim 67 wherein the step of providing said at least a second pair of data path circuit comprises:

providing a plurality of write driver circuits connectable to said sense amplifier circuits, each of said write driver circuits having a data write line for inputting data into said sense amplifier circuits; and

providing a plurality of read driver circuits connectable to said sense amplifier circuits, each of said read driver circuits having a data read line for outputting data from said sense amplifier circuits.

70. The memory circuit of claim 67 wherein each block of memory cells includes two row decoders located on opposite sides of said block, said row decoders respectively activating alternate word lines within said block.