A signal processing circuit includes a main input sampling structure with an integrator operational amplifier and input lines including a switched capacitor. The input lines have switched connections to input signal lines and reference signal lines. A replica sampling structure is used in combination with the main input sampling structure to eliminate or reduce signal-dependent current that is drawn from the input signal line and the reference signal line. The replica sampler includes buffered input lines and switched capacitor of the input sampling structure but the capacitors have switched connections to the reference signal lines such that the connections have opposite polarity to the connections of the reference signal line to the input sampling structure. The replica sampler eliminates or reduces signal-dependent current from the reference signal lines. Buffering of the input lines in the replica sampler eliminates or reduces the signal-dependent current drawn from the input signal lines. The structure efficiently allows the use of a smaller capacitance for the same performance.
The present invention provides a method and apparatus to define and sustain such a physical level by connecting the output through a transmission gate to an input pin. For a certain state of the output, one level of an input may be fed through to the output to generate an output voltage level. In the preferred embodiment of the present invention, a chip select signal CS is used to define a low level logic signal. An control logic selectively switches a high level logic signal voltage (e.g., V+supply voltage) or the low level logic signal voltage (CS) to produce an output digital logic signal. In a further embodiment of the present invention, separate logic level signals IN.sub.H and IN.sub.L may be selectively switched by control logic to generate an output logic level signal independent of supply voltages V+ and V-.
A Built-In Self-Test (BIST) circuit is employed to automatically test integrated analog to digital converters (ADC). Proposed technique applies delta-sigma (.DELTA..SIGMA.) modulator concept to ADC testing and results in a fully automated accurate test procedure suitable for differential non-linearity (DNL) and integral non-linearity (INL) testing. Additional analog circuitry does not have a significant effect on the test accuracy and the test resolution is determined by the sampling frequency of the delta-sigma modulator.
A low-noise switching voltage regulator for supplying a voltage to a radio frequency (RF) power amplifier is disclosed. In one embodiment, the invention can be conceptualized as a power amplifier supply circuit, comprising a pair of oppositely polarized semiconductor switches, and a data formatter configured to supply a data stream having a voltage transition on at least every other bit to each of the pair of oppositely polarized semiconductor switches.
A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said second capacitor to said first summing node of said amplifier to provide third and fourth output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, the combined first, second, third and fourth changes representing the capacitance of said first and second capacitors substantially independent of said input common mode voltage.
An analog-to-digital converter is provided for converting multiple analog inputs into corresponding digital values. An output interface circuit uses differential signaling to reduce noise and interference induced in the analog portions of the analog-to-digital converter.
