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| United States Patent | 6153519 |
| Link to this page | http://www.wikipatents.com/6153519.html |
| Inventor(s) | Jain; Ajay (Austin, TX), Weitzman; Elizabeth (Austin, TX) |
| Abstract | A refractory Metal Nitride and a refractory metal Silicon Nitride layer
(64) can be formed using metal organic chemical deposition. More
specifically, tantalum nitride (TaN) (64) can be formed by a Chemical
Vapor Deposition (CVD) using Ethyltrikis (Diethylamido) Tantalum (ETDET)
and ammonia (NH.sub.3). By the inclusion of silane (SiH.sub.4), tantalum
silicon nitride (TaSiN) (64) layer can also be formed. Both of these
layers can be formed at wafer temperatures lower than approximately
400.degree. C. with relatively small amounts of carbon (C) within the
film. Therefore, the embodiments of the present invention can be used to
form tantalum nitride (TaN) or tantalum silicon nitride (TaSiN) (64) that
is relatively conformal and has reasonably good diffusion barrier
properties. |
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Title Information  |
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| Publication Date |
November 28, 2000 |
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| Filing Date |
March 31, 1997 |
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Title Information  |
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References  |
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U.S. References |
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| | Reference | Relevancy | Comments | Reference | Relevancy | Comments | 5913144 Niguyen et al.
Jun,1999 |      Your vote accepted [0 after 0 votes] | | 5731220 Tsu et al.
Mar,1998 |      Your vote accepted [0 after 0 votes] | | 5675310 Wojnarowski et al.
Oct,1997 |      Your vote accepted [0 after 0 votes] | | 5668054 Sun et al.
Sep,1997 |      Your vote accepted [0 after 0 votes] | | 5559047 Urabe
Sep,1996 |      Your vote accepted [0 after 0 votes] | | 5364803 Lur et al.
Nov,1994 |      Your vote accepted [0 after 0 votes] | | 5352623 Kamiyama
Oct,1994 |      Your vote accepted [0 after 0 votes] | | 5273783 Wanner
Dec,1993 |      Your vote accepted [0 after 0 votes] | | 5252518 Sanhdu et al.
Oct,1993 |      Your vote accepted [0 after 0 votes] | | 5200028 Tatsumi
Apr,1993 |      Your vote accepted [0 after 0 votes] | | 5066615 Brady et al.
Nov,1991 |      Your vote accepted [0 after 0 votes] | | 4977100 Shimura
Dec,1990 |      Your vote accepted [0 after 0 votes] | | 4847111 Chow et al.
Jul,1989 |      Your vote accepted [0 after 0 votes] | | 4684542 Jasinski et al.
Aug,1987 |      Your vote accepted [0 after 0 votes] | | 4490209 Hartman
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| | Reference | Relevancy | Comments | MH. Tsai et al., "Metal-organic chemical vapor deposition of tantalum nitride barrier layers for ULSI applications", XP 000595265, Thin Solid
Films 270(1995) 531-536, pp. 531-536.
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Paul Martin Smith et al., "Chemical Vapor Deposition of Ternary Refractory Nitrides for Diffusion Barrier Applications", XP-002123863, Jun. 1996 VMIC Conf. (ISMIC), pp. 162-167.
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Shah; "Refractory Metal Gate Processes for VLSI Applications"; IEEE Transactions on Electron Devices, vol. ED-26, No. 4; pp. 631-40 (1979).
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Sun, et al.; "Diffusion Barrier Properties of CVED Tantalum Nitride for Aluminum and Copper Interconnections"; VMIC Conf; 1995 ISMIC; pp. 157-62.
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Tsai, et al. Metalorganic chemical vapor deposition of tantalum nitrid by tertbutylimidortis (diethylamido) tantalum for advanced metalization; Appl Phys Lett 67 (8); pp. 1128-130; (1995).
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Fix, et al.; "Chemical Vapor Deposition of Vandium, Niobium, and Tantalum Nitride Thin Films"; Chem. Mat. vol. 5; pp. 614-619 (1993).
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Campbell, et al.; "MOSFET Transistors Fabricated with High Permitivity TiO2 Dielectrics"; IEEE Transactions on Electon Devices; vol. 44, No. 1; pp. 104-09; Jan. 1997.
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Akasaka et al.; "Low-Resistivity Poly-Metal Gate Electrode Durable for High-Temperature Processing"; IEEE Transactions on Electron Devices; vol. 43, No. 11; pp. 1864-68; (1996).
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Hubbard et al., "Thermodynamic Stability of Binary Oxides in Contact with Silicon"; Mat. Res. Soc. Symp. Proc. vol. 401; pp. 33-39 (1996).
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | He, et al.; "Microstructure and properties of Ti-Si-N films prepared by plasma-enhanced chemical vapor deposition"; Materials Chemistry and Physics; 44; pp. 9-16 (1996).
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Sun, et al."A Comparative Study of CVD Tin and CVD TaN Diffusion Barriers for Copper Interconnection"; IEEE 1995 Int'l Electron Devices Meeting Technical Digest; pp. 461-64 (1995).
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Kasai, et al.;"W/WNx/Poly-Si Gate Technology for Future High Speed Deep Submicron CMOS LSIs"; IEDM; pp. 497-500 (1994).
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Reid, et al.; Evaluation of amorphous (Mo, Ta, W)-Si-N diffusion barriers for <Si>ICu metallizations; Thin Solid Films, vol. 236; pp. 319-24; (1993).
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Wang, et al.; "Diffusion barrier study on TaSix and TaSixNy"; Thin Solid Films,; vol. 235; pp. 169-74 (1993).
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Shizhi, et al., "Ti-Si-N Films Prepared by Plasma-Enhanced Chemical Vapor Deposition"; Plasma Chemistry and Plasma Processing; vol. 12, No. 3; pp. 287-97 (1992).
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Wright, et al.; "The Effect of Fluorine in Silicon Dioxide Gate Dielectrics"; IEEE Transactions of Electron Devices; vol. 36, No. 5; pp. 879-89 (1989).
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Onodera et al.; "A 630-mS/mm GaAs MESFET with Au/WSiN Refractory Metal Gate"; IEEE Electron Device Letters; vol. 9, No. 8; pp. 417-18 (1988).
. Jul,2007 |      Your vote accepted [0 after 0 votes] | | Chiou, et al.; "Microstructure and Properties of Multilayer-Derived Tungsten Silicide"; Journal of Electronic Materials, vol. 16; No. 4; pp. 251-55 (1987).. Jul,2007 |      Your vote accepted [0 after 0 votes] | | |
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Market Review  |
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Technical Review  |
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Claims  |
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We claim:
1. A method of forming a barrier layer comprising the steps of:
placing a semiconductor substrate into a chemical vapor deposition (CVD) reactor;
introducing a metal organic precursor into the (CVD) reactor;
introducing a semiconductor source into the (CVD) reactor; and
reacting the metal organic precursor, and the semiconductor source to form a refractory metal-semiconductor-nitride layer.
2. The method of claim 1, including an additional step of:
introducing ammonia into the CVD reactor; and wherein
the step of reacting includes reacting the ammonia, the metal organic precursor, and the semiconductor source to form a refractory metal-semiconductor-nitride layer.
3. The method of claim 2, wherein the step of introducing the ammonia further comprises the step of introducing the ammonia at a flow rate of approximately 200 to 500 standard cubic centimeter per minute.
4. The method of claim 1, wherein:
the step of introducing the semiconductor source includes the semiconductor source being silane.
5. The method of claim 1 wherein the step of introducing a metal organic precursor includes the metal organic precursor being [(R.sup.1).sub.2 N)].sub.3 -Ta.dbd.NR.sup.2, where R.sup.1 comprises an ethyl, and R.sup.2 comprises one of an ethyl, a
methyl, and hydrogen.
6. The method of claim 5, wherein the step of reacting forms a refractory metal-semiconductor-nitride layer having a carbon content of less than approximately 15 atomic percent.
7. The method of claim 1, wherein:
the step of placing includes placing the semiconductor substrate on a susceptor; and
the step of reacting is performed at a substrate temperature of no greater than approximately 400.degree. Celsius.
8. The method of claim 1, wherein the barrier layer is deposited using a plasma.
9. The method of claim 1, wherein the step of introducing a metal organic precursor comprises sub steps of:
flowing a carrier gas into an ampoule at a flow rate of approximately 200 to 800 standard cubic centimeters per minute; and
bubbling the carrier gas through the metal organic precursor, wherein the ampoule includes the metal organic precursor and a heater having a temperature of approximately 50.degree. Celsius to approximately 90.degree. Celsius.
10. A method of forming a barrier layer comprising the steps of:
placing a semiconductor substrate into a CVD reactor;
introducing a precursor into the CVD reactor, wherein:
the precursor comprises ((R.sup.1).sub.2 N)).sub.3 -Ta.dbd.NR.sup.2 ;
R.sup.1 comprises an ethyl; and
R.sup.2 comprises one of an ethyl, a methyl, and hydrogen;
introducing ammonia into the CVD reactor;
introducing silicon into the CVD reactor; and
reacting the precursor, ammonia, and silicon to form a conductive layer containing tantalum silicon nitride.
11. The method of claim 10, wherein the step of reacting further comprises the layer containing tantalum and nitrogen having a step coverage of greater than approximately 50%.
12. The method of claim 11, wherein the step of reacting further comprises the step coverage of greater than 50% occurring in a feature having an aspect ratio of approximately 3:1 or greater.
13. The method of claim 10, wherein the step of reacting further comprises the layer containing tantalum and nitrogen having a carbon content of less than approximately 10 atomic %.
14. The method of claim 10, wherein the step of reacting includes a sub step of:
maintaining a wafer temperature of less than approximately 400.degree. Celsius.
15. The method of claim 14, wherein the barrier layer is deposited using a plasma.
16. The method of claim 10, further comprising the step of:
performing an in-situ plasma treatment after the step of reacting, wherein the in-situ plasma treatment reduces the resistivity of the layer containing tantalum and nitrogen.
17. A method of forming a semiconductor device comprising the steps of:
forming a first insulation layer over a semiconductor device substrate, wherein the first insulation layer has an opening;
forming an interconnect within the opening, wherein the interconnect is formed by:
depositing a first refractory metal-semiconductor-nitride layer using chemical vapor deposition; and
forming a first conductive layer after the first refractory metal-semiconductor-nitride layer, wherein the first conductive layer comprises aluminum or copper.
18. The method of claim 17, wherein the step of forming the first conductive layer includes the first conductive layer contacting the refractory metal-semiconductor-nitride layer.
19. The method of claim 17, wherein the step of forming includes the conductive layer forming a physical contact with the refractory metal-semiconductor-nitride layer.
20. The method of claim 19, wherein the step of forming includes the conductive layer forming an electrical contact with the refractory metal-semiconductor-nitride layer.
21. The method of claim 19, further comprising the steps of:
forming a second insulation layer prior to the formation of the first insulation layer, wherein the second insulation layer has an opening;
depositing a refractory metal layer after the step of forming a second insulation layer and prior to the formation of the first insulation layer;
depositing a second refractory metal-semiconductor-nitride layer using chemical vapor deposition after the step of depositing the refractory metal layer and prior to the formation of the first insulation layer; and
depositing a second conductive layer after the step of depositing the second refractory metal and prior to the formation of the first insulation layer.
22. The method of claim 21, wherein the step of depositing a refractor metal includes the refractory metal layer comprising a titanium layer.
23. The method of claim 21 wherein the step of forming a second insulation layer includes the opening of the second insulation layer exposing a substrate region.
24. The method of claim 23, wherein the step of forming a second insulation layer includes the substrate region being a silicon substrate region.
25. The method of claim 21 wherein the step of forming a first insulation layer includes the opening of the first insulation layer overlapping the opening of the second insulation layer.
26. The method of claim 1, wherein the barrier layer is part of an interconnect.
27. The method of claim 10, wherein the barrier layer is part of an interconnect. |
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Claims  |
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Description  |
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FIELD OF THE INVENTION
The present invention relates generally to the processing of semiconductor devices, and more specifically to providing a diffusion barrier onto a semiconductor device.
BACKGROUND OF THE INVENTION
Modern semiconductor devices are requiring speeds in excess of 200 megahertz. In order to form future generations of semiconductor devices, copper (Cu) will essentially be required for interconnects. One problem with the use of copper is that
copper cannot directly contact silicon dioxide because copper diffuses too easily through the silicon dioxide layer. Therefore, in the prior art the copper is typically surrounded by a diffusion barrier on all sides.
Diffusion barriers for copper include a number of materials, such as silicon nitride and various refractory metal nitrides (TiN, TaN, WN, MoN) and refractory silicon nitrides (TiSiN, TaSiN, WSiN), or refractory metal-semiconductor-nitride layers. Of all of these barriers, the two showing promise for barriers include tantalum nitride (TaN) and tantalum silicon nitride (TaSiN). These materials are usually deposited by sputtering. However, sputtering generally has poor sidewall step coverage,
where step coverage is defined to be the percentage of a layer being deposited on a specific surface divided by the thickness of a layer being deposited on the uppermost surface of a semiconductor device. In the case of sputtered tantalum nitride (TaN)
and tantalum silicon nitride (TaSiN), and the step coverage for a 0.35 .mu.m via can be in the range of 5% to 20% for an aspect ratio of 3:1. Such low step coverage increases the risk that the barrier material will not be thick enough to be an effective
diffusion barrier along the sides and bottom of a deep opening. In an attempt to get enough of the material along the walls of openings, a much thicker layer at the uppermost surface is deposited, however, this is undesirable because it increases the
resistance of the interconnect.
Chemical vapor deposition (CVD) has been used to form tantalum nitride. The precursors for TaN includes tantalum halides, such as Tantalum Pentachloride (TaCl.sub.5). The problem with tantalum halides is that the halides react with the copper
causing interconnect corrosion. Another precursor includes penta[dimethylamido]tantalum (Ta(NMe.sub.2).sub.5). When this precursor is used to deposit tantalum nitride (TaN), the compound that is actually forms is an insulating layer of Ta.sub.3
N.sub.5. An insulator cannot be used in contact openings or via openings because the insulator prevents electrical contact between the upper interconnect layer and the lower interconnect layer.
Still another known precursor includes terbutylimido-tris-diethyl amino tantalum [(TBTDET), Ta.dbd.NBu(NEt.sub.2).sub.3 ]. This compound can be used to form TaN. However, there are problems associated with this precursor. Specifically,
deposition temperatures higher than 600.degree. C. is needed to deposit reasonably low resistivity films. Such high temperatures for back-end metallization are incompatible for low-k dielectrics and also induces high stresses due to thermal mismatch
between the back-end materials. Another problem with the TBTDET precursor is that too much carbon (C) is incorporated within the layer. This compound generally has approximately 25 atomic percent carbon. The relatively high carbon content makes the
layer highly resistive, and results in films that are less dense, lowering the diffusion barrier effectiveness for a comparable thickness of other materials. The resistivity of TaN when deposited using TBTDET at temperatures lower than 600.degree. C.
is approximately 12,000 .mu.ohm-cm. Films with such a high resistivity (desired is less than approximately 1000 .mu.ohm-cm) cannot be used for making effective interconnect structures.
CVD of titanium silicon nitride (TiSiN) has been demonstrated using titanium tetrachloride (TiCl.sub.4). This compound is again undesirable because in forming the TiSiN, chlorine is once again present which causes corrosion of copper and other
materials used for interconnect.
A need, therefore, exists to deposit a TaN or TaSiN using organometallic precursors that can be formed relatively conformally with a reasonable resistivity and good barrier properties at lower wafer temperatures.
BRIEF DESCRIPTION OF THE
DRAWINGS
The present invention is illustrated by way of example and not limited in the accompanying figures, in which like references indicate similar elements, and in which:
FIG. 1 includes an illustration of a cross-sectional view of a portion of semiconductor device substrate after forming openings in an interlevel dielectric layer to doped regions within the substrate;
FIG. 2 includes an illustration of a cross-sectional view of FIG. 1 after forming materials needed to form interconnects in accordance with one embodiment of the present invention;
FIG. 3 includes an illustration of a substrate of FIG. 2 after forming inlaid interconnects to doped regions within the substrate;
FIG. 4 includes an illustration of a top view of the substrate of FIG. 3. after forming an interlevel dielectric layer and an opening within that layer;
FIG. 5 includes an illustration of a cross-sectional view of the substrate of FIG. 4 illustrating the opening to the lower interconnect;
FIG. 6 includes an illustration of a cross-sectional view of the substrate of FIG. 5 after forming an interconnect to a lower interconnect level; and
FIG. 7 includes in illustration of a cross-sectional view of the substrate of FIG. 6 after forming a substantially completed device.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity, and
have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures are exaggerated relative to other elements to help to improve understanding of embodiment(s) of the present invention.
DETAILED DESCRIPTION OF THE DRAWINGS
A refractory Metal Nitride and a refractory metal Silicon Nitride layer are formed using metal organic chemical deposition. More specifically, tantalum nitride (TaN) can be formed by a Chemical Vapor Deposition (CVD) using Ethyltrikis
(Diethylamido) Tantalum [(ETDET), (Et.sub.2 N).sub.3 Ta.dbd.NEt] and ammonia (NH.sub.3). By the inclusion of a semiconductor source such as silane (SiH.sub.4), a tantalum silicon nitride (TaSiN) layer can also be formed. Both of these layers can be
formed at wafer temperatures lower than 500.degree. Celsius with relatively small amounts of carbon (C) within the film. Therefore, the embodiments of the present invention can be used to form tantalum nitride (TaN) or tantalum silicon nitride (TaSiN)
layer that is relatively | | |