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Electronic sampling circuit
   
Document Number
US Patent 6154159
Issued Date
November 28, 2000
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Abstract
An electronic sampling circuit for determining redox potentials, and consequently specie concentration, in a photographic solution, applies a linear ramp of a square wave voltage to a first electrode (6) immersed in the solution. The current drawn by an adjacent electrode (12) is converted to a voltage for sampling. A pair of sample-and-hold circuits (40,42) store signals sampled at the peak and adjacent trough respectively of a square wave pulse, and a subsequent analogue difference circuit (44) subtracts the two signals. The resulting signal is converted to a digital code by a low cost, low bit count analogue-to-digital converter (46), which is stored on a microprocessor (48). The sampling process is repeated for successive square waves along the ramp. This circuit configuration enables the difference between analogue signals to be measured where the signals differ in amplitude by small amounts but have a wide dynamic range, without the need for an expensive, high bit count analogue-to-digital converter.
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Number of Claims:
5
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Owner
Eastman Kodak Company (Rochester, NY)
Published
November 28, 2000
Application Number
09/129,815
Filed
August 6, 1998
US Classification
341/122   341/155
Int'l Classification
H03M   3/04   (20060101)   H03M   3/00   (20060101)   H03M   1/12   (20060101)  
Examiner
Attorney/Law Firm
Priority Data
Aug 16, 1997 [GB] 9717324
USPTO Field of Search
341/122   341/131   341/132   341/139   341/141   341/143  
Related Patents
6614378 - Sampling processing device and imaging apparatus using it - Owned by Sony Corporation (Tokyo,JP)

A sample-and-hold circuit and an analog-to-digital conversion circuit are provided, and a latch circuit is provided downstream of the analog-to-digital conversion circuit. For example, a correlated double sampling (CDS) circuit is configured in which a first latch circuit is disposed downstream of the analog-to-digital conversion circuit and a second latch circuit is disposed downstream of the first latch circuit. Delayed output signals of the respective latch circuits are sent to a calculation section, which takes subtraction between those output signals. Resulting data is output via another latch circuit.

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Description
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