 |
Description  |
|
|
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to digital processing techniques, and more particularly to a recursive digital filter having internal nodes which are reset to avoid a continued DC offset.
2. Background of Related Art
Efficient and inexpensive digitization of telephone grade audio has been accomplished for many years by an integrated device known as a "codec." A codec (short for COder-DECoder) is an integrated circuit or other electronic device which combines
the circuits needed to convert analog signals to and from Pulse Code Modulation (PCM) digital signals.
Early codecs converted analog signals at an 8 KHz rate into 8-bit PCM for use in telephony. More recently, the efficiency and low cost advantages of codecs have been expanded to convert analog signals at a 48 KHz sampling rate into 16-bit stereo
(and even up to 20-bit stereo) for higher quality use beyond that required for telephony. With higher quality audio capability, today's codecs find practical application in consumer stereo equipment including CD players, modems, computers and digital
speakers.
With the development of codecs for these more sophisticated purposes came the need to improve the analog signal-to-noise (S/N) ratio to at least 75 to 90 dB. Improved S/N ratios have been achieved largely by separating the conventional codec
into Two individual sub-systems and/or two separate integrated circuits (ICs): a controller sub-system handling primarily the digital interface to a host processor, and an analog sub-system handling primarily the interface to, mixing and conversion of
analog signals. This split digital/analog architecture has been documented most recently as the "Audio Codec '97 Component Specification", Revision 1.03, Sep. 15, 1996, as revised in "Audio Codec '97", Revision 2.0, Sep. 29, 1997 (collectively referred
to herein as "the AC '97 specification"). The AC '97 specification in its entirety is expressly incorporated herein by reference.
FIG. 1 is a generalized block diagram of a conventional split-architecture audio codec conforming to the AC '97 specification. Audio codecs conforming to the AC '97 specification accommodate audio sources from CD players, auxiliary devices such
as stereo equipment, microphones and/or telephones.
As shown in FIG. 1, currently known split-architecture audio codecs contemplate a host processor, an audio codec (AC) controller sub-system or IC 402, and an AC analog sub-system or IC 404. The connection between the AC controller sub-system 402
and the AC analog sub-system 404 is currently defined as a five-wire time division multiplexed (TDM) interface controlled by an AC-link 406 in the AC analog sub-system 404. The AC controller sub-system 402 may be a stand alone device, or it may be a
portion of a larger device such as a Peripheral Component Interconnect (PCI) interface device. PCI is a processor-independent, self-configuring local bus. Alternatively, the AC controller sub-system 402 may be a part of a central processing unit (CPU).
Because of the capabilities of the split digital/analog architecture (i.e., AC controller sub-system 402 and AC analog sub-system 404), the AC '97 specification includes a significant amount of flexibility intended to capture a large market by
satisfying many consumer-related audio needs. For instance, the conventional AC analog sub-system 404 includes interface capability to accept input From multiple sources and to mix the analog signals from those multiple sources. Possible analog signal
sources include a CD, video, or telephone line.
FIG. 2A is a diagram showing relevant features of the conventional AC analog sub-system 404. The relevant features include an analog mixing and gain control section 200 accepting input from various analog audio sources 210 including a PC Beep
signal, a telephone input, two microphone inputs, a general line in, a signal from a CD player, an analog signal from a video source, and an auxiliary input. The analog mixing and gain control section 200 mixes analog signals input from the various
analog audio sources 210, and outputs up to three separate analog channels for digitization in analog-to-digital (A/D) converters 206a, 206b, 206c. A digital interface 202 prepares the mixed, digitized audio signals output from the A/D converters
206a-206c into a serial data stream for transmission via an AC link 406.
In the opposite direction, digital audio signals received from the serial data stream of the AC link 406 by the digital interface 202 are converted back into analog audio signals by digital-to-analog (D/A) converters 204a, 204b, and output to the
analog mixing and gain control section 200 for gain control and output on the various desired analog audio source lines 210.
FIG. 2B is a more detailed schematic diagram of the analog mixing and gain control section 200 of the AC analog subsystem 404 shown in FIG. 2A. In FIG. 2B, the analog signals from the analog audio sources 210 are gain adjusted in analog form by
analog gain adjusters 300, then mixed in analog mixer 310. A secondary analog mixer 312 allows the inclusion of the PC beep signal and telephone signal into the mixed analog product. The mixed analog signal is gain adjustable in gain adjuster 302 and
output from the Analog mixing and gain control block 200 and AC analog subsystem 404. Analog mixer 314 mixes the left and right channels of the summed analog signal to provide a mono signal output, which is gain adjusted in analog gain adjuster 304.
Analog mixer 316 similarly provides a mono output from the stereo output signal.
For recording, a multiplexer (MUX) 320 multiplexes signals from the various sources and allows selection of one per channel of the various sources together with a microphone signal for output to a master analog gain adjuster 306. The three gain
adjusted analog signals output from MUX 320 are finally converted into digital signals by A/D converters 206a, 206b and 206c. Thus, the mixing and gain control of a conventional AC analog subsystem 404 is typically handled with analog circuitry.
While it is suitable to mix and gain adjust audio signals in analog form for certain applications as shown in FIGS. 2A and 2B, analog features on an integrated circuit require significant amounts of space in the AC analog subsystem 404. Analog
circuitry also generally provides a larger source of electrical noise causing cross-talk or other disadvantageous side effects. Thus, to improve a signal to noise ratio of output signals, it is desirable to provide digital testing arid processing
techniques, e.g., to minimize the analog circuitry in the AC analog subsystem.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a digital filter comprises a recursive stage, and an output stage in series with the recursive stage. At least one of the recursive stage and the output stage including a reset input
line configured to be activated upon a detection of an unstable condition with respect to a framing signal indicating a start of a data frame.
A method of resetting a digital filter in accordance with the present invention includes detecting an instability in a framing signal. A latch is reset in at least one stage of the digital filter based on the detection of the instability.
BRIEF DESCRIPTION OF THE DRAWINGS
Features and advantages of the present invention will become apparent to those skilled in the art from the following description with reference to the drawings, in which:
FIG. 1 shows a conventional split-architecture audio codec.
FIG. 2A shows a conventional audio functional module of a conventional audio codec shown in FIG. 1.
FIG. 2B shows a conventional analog mixing and gain control functional module of a split-architecture audio codec as shown in FIGS. 1 and 2.
FIG. 3 shows relevant features of an AC analog subsystem in accordance with the principles of the present invention.
FIG. 4 is a more detailed schematic diagram showing the relevant features of the AC analog subsystem shown in FIG. 3.
FIGS. 5A(1) and 5A(2) are detailed block diagrams of a filter and gain adjust module in an A/D direction and a D/A direction, respectively, according to the present invention.
FIG. 5B shows in more detail a filter and gain adjust of the embodiment of the present invention shown in FIG. 4.
FIG. 6A shows a conventional SINC filter having separate taps.
FIG. 6B shows a recursive SINC filter in accordance with the present invention.
FIG. 7 shows in more detail an embodiment of the count detector for generating a reset signal to a SINC.sup.3 filter in accordance with another aspect of the present.
FIGS. 8A and 8B are timing diagrams for the count detector of the FIR filters shown in FIG. 7.
FIG. 9 shows an overflow/clamp circuit as applied to the disclosed embodiment of the present invention.
FIGS. 10A and 10B show an overflow/clamp circuit in accordance with another aspect of the present invention.
FIGS. 11A(1) and 11A(2) show logic for detecting overflow in an embodiment of the circuit of FIGS. 10A and 10B.
FIG. 11B shows in more detail an embodiment of the overflow/clamp circuit shown in FIGS. 10A and 10B.
FIGS. 12A and 12B are logic diagrams for the overflow/clamp circuit shown in FIG. 11B.
FIG. 13 is a timing diagram showing four cycles of a clock for use in each stage of an Infinite Impulse Response (IIR) filter in an embodiment of the present invention
FIGS. 14A, 14B and 14C are more detailed diagrams showing the implementation of six channels of 4 stage (i.e., 8.sup.th order) IIR filters in the embodiment of the present invention.
FIG. 15 is a schematic block diagram showing a six channel, 8.sup.th order IIR filter in accordance with the embodiment of the present invention.
FIG. 16 shows one technique for initializing random access memory (RAM) for storing state variables for a digital IIR filter.
FIG. 17 shows an improved technique for initializing random access memory for storing variables for a digital IIR filter in accordance with another aspect of the present invention.
FIG. 18A(1) is a more detailed block diagram showing one embodiment of the state variable RAM address bus generator shown in FIG. 15.
FIG. 18A(2) is a more detailed block diagram showing another embodiment of the state variable RAM address bus generator shown in FIG. 15.
FIG. 18B(1) is a schematic diagram of the embodiment of the state variable RAM address bus generator shown in FIG. 18A(1).
FIG. 18B(2) is a schematic diagram of the embodiment of the state variable RAM address bus generator shown in FIG. 18A(2).
FIG. 19 shows a circuit for inserting test bit patterns between digital functional modules in an integrated circuit.
FIG. 20 shows a circuit for inserting test bit patterns into a digital circuit in accordance with another aspect of the present invention.
FIGS. 21A and 21B are detailed circuit diagrams showing output latches within functional modules shown in FIG. 20.
FIG. 22A is a more detailed circuit diagram showing an embodiment of the test node controller shown in FIG. 20.
FIG. 22B is a logic table for the input, output and controlled latch output, for the test node controller shown in FIGS. 20-22A.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
The present invention relates in general to digital testing filtering and other digital functions, e.g., performed between the digitization of analog audio signals and the transmission of the digitized signals over a communication link. While
the present invention is described with respect to specific embodiments relating to a split-architecture audio codec in conformance with the AC '97 specification, it relates to digital data testing, processing and filtering in general.
FIG. 3 shows relevant features of an AC analog subsystem of a split-architecture audio codec in accordance with the principles of an embodiment of the present invention.
In FIG. 3, an AC analog subsystem 390 includes a digital interface 352, a digital filter and gain module 357 including six channels of gain control 356a, 356b, and six channels of digital filtering 360a, 360b, a digital mixing and gain control
module 354, three D/A converters 370a, 370b, 370c, and three A/D converters 378a, 378b, 378c.
The digital interface 352 receives three digital audio signals from the AC link 406 (i.e., left, right and monaural ("mono")), and outputs the same to three channels of the digital gain control module 356a operating in a D/A direction. The
digital gain control module 356a provides programmable gain to the digital signals of each channel. For instance, in the disclosed embodiment, between +12 to -46.5 decibels (dB) (i.e., attenuation) of gain, e.g. in 1.5 dB steps, is provided to the
digital audio signals before they are each output to appropriate channels of a digital filter module 360a for filtering. After filtering, the three channels of digital audio signals are input to the mixing and gain control module 354 for mixing and
additional gain control, if desired. After appropriate mixing with other signals as desired, and after appropriate gain control (e.g., attenuation), the digital audio signals are converted into analog signals in D/A converters 370a, 370b, 370c, and
output from the AC analog subsystem 404 (FIG. 2A).
FIG. 4 shows the circuit of FIG. 3 in more detail. FIG. 4 shows details of the digital processing both in an A/D direction (upper portion of FIG. 4), and in a D/A direction (lower portion of FIG. 4).
In the A/D direction of FIG. 4, a left (L) and right (R) channel of either a LINE IN signal or a CD signal are selected by multiplexers (MUXs) 402, 403 for input to analog gain modules 405, 406. The analog gain modules 405, 406 are formed by
programmable gain adjust modules in the disclosed embodiment, and provide an analog gain of between 0 and 12 dB. Of course, analog gain can be provided in any conventional form, and may alternatively be eliminated entirely, particularly if full
conformance with the AC '97 specification is not required in audio codec applications.
The analog signals are output from the analog gain modules 05, 406 to .SIGMA./.DELTA. A/D converters 408, 410, respectively, for digitization. The disclosed .SIGMA./.DELTA. A/D converters 408, 410 input analog signals in a range of 0 to 5
volts and output 1-bit .SIGMA./.DELTA. data at a 12.288 megabit per second (Mb/s) rate. However, it is to be understood that the particular data encoding techniques, analog signal range, sample size and data rate are exemplary only. Aspects of the
present invention are equally applicable to differing data encoding techniques, analog signal ranges, sample sizes, and/or data rates.
The left, right, monaural and other audio signals digitized in the A/D direction pass through a bank of digital gain adjusters 420, which each provide a gain adjustment, e.g., of between 0 and -46.5 dB (i.e., an attenuation) for digital signals
in respective digital channels, -46.5 dB essentially providing a mute of that audio path. Both banks of digital .SIGMA./.DELTA. gain adjusters 420, 464 provide gain adjustment to input digital signals, e.g., to 1-bit .SIGMA./.DELTA. encoded audio
data.
The AC '97 specification requires at least between +12 dB and -46.5 dB of gain in each channel. In the disclosed embodiment, which is in general conformance with the AC '97 specification, positive gain is accomplished in the analog gain modules
405, 406, and negative gain is distributed among several digital gain adjustment modules, first in the gain adjuster module 420, then after summation of left and right channels in digital .SIGMA./.DELTA. mixers 444 and 446 in master channel gain
adjusters 430 and 432, and then in the digital filters/gain adjust modules 434, 436 and 428. The master channel gain adjusters 430, 432 and 426 provide a gain adjust of between 0 and -46.5 dB. Of course, but for conformance with the AC '97
specification, any or all of the gain control may be consolidated into fewer modules, distributed over more modules, increased, decreased, and/or eliminated as desired.
Two microphone signals MIC1, MIC2 are input to a multiplexer 412 for selection of either microphone input signal MIC1, MIC2 for further processing. The selected microphone signal output from the microphone MUX 412 passes through two programmable
gain adjust modules (not shown), one providing a gain of between 0 and 12 dB, and the other providing a gain of between 0 and 32 dB, and optionally through a filter 416, before being digitized by .SIGMA./.DELTA. A/D converter 414.
Inventively, preferably all positive gain desired in a particular channel is accomplished before digitization. However, because each input channel (e.g., the microphone path 415) may be digitized and fed to as many as five separate destination
paths (e.g., microphone destination paths 415a to 415e), this would require as many as five A/D converters each having as many as five corresponding gain adjusters. The present embodiment simplifies the requirements to only a single gain adjuster before
a single A/D converter in each input path.
For instance, in the microphone path, instead of the single gain module 416 shown in FIG. 4 placed before the A/D converter 414, conventional techniques would have otherwise required five separate gain modules in each of the destinations
415a-415e. Thus, because each channel may have a different gain value fed to each of a plurality of destinations (e.g., to the left record, right record, mono output, left playback, and right playback), conventional techniques dictate the use of a
plurality of separate gain modules for each input. This is undesirable, inter alia, because it requires a significantly larger amount of circuitry.
Instead, as shown in FIG. 4 in accordance with the principles of this embodiment, a single gain adjuster, e.g., 416, in the microphone path 415, is placed in each path. The single gain adjuster 416 handles all overall positive gain for all of
the destinations. The single gain adjuster, e.g. 416, is preferably placed in an analog path, e.g., before the A/D converter 414 for the microphone path 415, to take advantage of the lower noise floor before digitization.
The single gain adjuster, e.g., 416, is programmed to provide an amount of positive gain equal to the highest required for any of its output paths, e.g., 415a-415e. Then, to provide flexibility in each channel utilizing the gain adjusted
digitized signal, suitable amounts of attenuation is added in subsequent gain adjusters, e.g., 420, 426 and/or 464, to attenuate the digitized signal back down to the desired level.
For instance, if the user of the device programs registers requiring gain for the microphone path 415 as follows:
TABLE I ______________________________________ PATH OVERALL GAIN ______________________________________ Record Right +12 dB Record Left +6 dB Record Mic +3 dB Play Right -3 dB Play Left -9 dB ______________________________________
Then the single gain adjuster 416 is programmed to provide +12 dB of gain for all destinations 415a-415e. Thereafter, suitable attenuation is programmed in any subsequent gain adjuster to reduce the overall gain back to the desired level. For
instance, the Record Right path would not have any attenuation added subsequently, the Record Left path would attenuate by 6 dB, e.g., in the corresponding gain adjuster in bank 420, the Record Mic path would attenuate by 9 dB, e.g., in the corresponding
gain adjuster in bank 420, the Play Right path would attenuate by 15 dB, e.g., in a corresponding gain adjuster in bank 464, and the Play Left path would attenuate by 21 dB, e.g., in a corresponding gain adjuster in bank 464.
If no destination path, e.g., 415a-415e requires positive gain, then the single gain adjuster, e.g., 416, is set to provide 0 gain.
The use of a single gain adjuster instead of a plurality of gain adjusters also simplifies the effort by a processor to change gain settings in each gain adjuster, e.g., on a frame-by-frame basis.
A processor such as a microcontroller can be implemented to control the various gain adjusters. For instance, a microcontroller can interpret the overall gain stored in registers by a user, placing all positive gain in the most suitable gain
adjusters, e.g., before digitization, and to distribute attenuation among other gain adjusters in the various paths.
The audio codec may also include provisions for input from other audio sources such as a telephone. For instance, a conditioned signal PH.sub.-- RECEIVE or a telephone line type signal PH.sub.-- HYBRID may be input to a down-line phone (DLP)
interface 418, which includes a hybrid for the telephone line signal. The monaural telephone signal is digitized in a .SIGMA./.DELTA. A/D converter 422.
The output from either the microphone .SIGMA./.DELTA. A/D converter 414 or the telephone .SIGMA./.DELTA. A/D converter 422 is selected in MUX 424 for gain adjustment in gain adjuster 426, and filtering and gain adjustment in digital filter and
gain adjuster 428, before being output to the digital interface 352 (FIG. 3).
In the A/D direction as shown in FIG. 3, three channels of analog input signals (e.g., left, right and microphone) are digitized in A/D converters 378a, 378b, 378c. In the disclosed embodiment, the analog signals are in a range of between 0 and
5 volts, but of course may be any appropriate voltage range. The three channels of digital signals from the A/D converters 378a-378c are mixed and gain controlled in three additional channels of the mixing and gain control module 354, where programmed
gain and mixing occurs as in the channels in the D/A direction. The resultant signals are output to the digital interface 352 for transmission on the AC serial link 406.
While it is possible to provide all gain control in a single module, the disclosed embodiment preferably distributes the gain control, e.g., between the mixing and gain control module 354 and again control modules 356a, 356b.
The disclosed D/A converters 370a-370c and A/D converters 378a, 378b, 378c are sigma/delta (.SIGMA./.DELTA.) converters accepting (D/A) and providing (A/D) 1-bit data samples at a desired sampling rate, e.g., 12.288 Mb/s. The digital
.SIGMA./.DELTA. mixers 444, 446, 466, 468 (FIG. 4) digitally mix the respectively input digital signals for the various sources. The digital signals are mixed, e.g., at data rates of 12.288 Mb/:3.
While 12.288 Mb/s is a preferred data rate for the .SIGMA./.DELTA. converter in the disclosed embodiment, it is in no way the only data rate possible. It is to be understood by those of skill in the art that this (and other) data rates
disclosed herein are by way of example only.
The digital processing within the mixing and gain control module 354, the digital filters 360a, 360b, and the gain control modules 356a, 356b is performed on the digital audio samples, e.g., .SIGMA./.DELTA. encoded digital data. Of course,
certain aspects of the present invention are equally applicable to processing data which is encoded using various techniques, not just .SIGMA./.DELTA., and having many sample sizes, not just 1-, 18- or 20-bit samples.
The disclosed audio codec embodiment utilizes .SIGMA./.DELTA. encoding to encode an analog signal into 1-bit samples. Sigma-delta (.SIGMA./.DELTA.) converters (sometimes referred to as delta-sigma (.SIGMA./.DELTA.) converters by those of skill
in the art) are well known. One advantage of using X/A D/A and A/D converters is to facilitate easy-to-manufacture digital circuitry along with low-precision analog circuitry, allowing for highly integrated D/A and A/D converters to be created primarily
with digital techniques. One conventional publication describing conventional .SIGMA./.DELTA. A/D and D/A converters is "Analog-to-Digital Conversion-A Practical Approach" by Kevin M. Daugherty, McGraw-Hill, Inc. (1994), which is expressly
incorporated herein by reference.
Similar circuitry is present for three channels in the opposite direction, i.e., in the D/A direction wherein digital audio channels from the digital interface 352 provide digital signals for output from the AC analog subsystem in analog form.
In this direction, in the disclosed embodiment, digital filter/gain adjusters 450, 452, 454 filter and gain adjust audio channels, e.g., the left, right and monaural channels, respectively, from the digital interface 352. The digital signals are
converted, e.g., into .SIGMA./.DELTA. encoded single bit samples in digital-to-digital .SIGMA./.DELTA. converters 456, 458, 460. A monaural MUX 462 selects between the mono signal from the digital interface 352 and the selected microphone input from
the microphone A/D .SIGMA./.DELTA. converter 414. A bank of gain adjusters 464 respectively digitally gain adjust individual channels, e.g., from 0 to -46.5 dB, and the gain adjusted output is summed in digital .SIGMA./.DELTA. mixers 466, 468. Master
gain adjusters 470, 472, 474 provide a gain adjustment, e.g., of 0 to -46.5 dB for each of the audio channels before conversion to analog in D/A .SIGMA./.DELTA. converters 482, 484, 486. The D/A .SIGMA./.DELTA. converters 482, 484, 486 each receive,
e.g., 12.288 MHz 1-bit .SIGMA./.DELTA. data and output an analog signal in a range, e.g., of between 0 and 5 volts.
Digital summer 477 adds signals from a left and right channel to form a monaural signal, which is gain adjusted in gain adjuster 480.
While FIGS. 3 and 4 show the processing of six digital audio channels, i.e., three in the A/D direction and three in the D/A direction, the present invention is equally applicable to any number of channels of digital processing in either the A/D
direction and/or the D/A direction.
Analog filters 488, 490, 492 provide analog filtering of the signals before output from the AC analog subsystem by rejecting out-of-band energy, e.g., audio signals beyond 20 KHz. For instance, in the disclosed embodiment, line out left, line
out right, and monaural signals are output from the AC analog subsystem. The analog filters 488, 490, 492 may be altered or eliminated as desired.
The digital filter/gain adjuster modules 434, 436, 428, 450, 452 and 454 form, e.g., six separate filter channels of a common digital filtering module 451. More or fewer channels may be provided as necessary to provide the desired number of
digital filter functions, but for conformance with the AC '97 specification. Each of the digital filter/gain adjuster channels 434, 436, 428, 450, 452, and 454 filters out or eliminates out-of-band (e.g., over 20 KHz) energy in the digital signal. The
filter channels also provide a decimation or interpolation function, decreasing or increasing the data rate, respectively. In the A/D direction, digital filter gain adjuster modules 434, 436, 428 provide a decimation of the data samples to a lower data
rate, while the digital filters 450, 452 and 454 in the D/A direction provide an interpolation of the data samples.
Each digital filter/gain adjuster module 434, 436, 428, 450, 452 and 454 comprises, e.g., two separate filters: A two-stage decimation finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. Preferably, after
filtering, the digital signal in each channel contains energy only in the desired range, e.g., in the 0 to 20 kilohertz (KHz) range, with a desired out-of-band rejection, e.g., of approximately at least -74 dB. Of course, the pass band and/or
out-of-band rejection level may be adjusted to suit particular applications. An FIR filter and an IIR filter are both utilized because they are complementary to one another. The IIR filter provides the desired out-of-band rejection, e.g., of at least
about -74 dB, but has repeating images at the filter rate, e.g., every 192 KHz. The FIR filter, while not contributing as significantly to the out-of-band rejection in the disclosed embodiment, eliminates the repeating images caused by the IIR filter.
A digital gain adjustment may be provided with the FIR filter and IIR filter in each channel. For instance, in the disclosed embodiment, a user programmable gain of either 0, -6, -12 or -18 dB is provided in each channel of the common digital
filtering modules 451. Of course, the digital gain adjustment may be eliminated, but for conformance with the AC '97 specification, if desired.
A primary purpose of the filters 434, 436, 428 in the A/D direction is decimation, and the primary purpose of the filters 450, 452, 454 in the D/A direction is interpolation. The FIR filter and IIR filter in each channel of the common digital
filtering module 451 in the A/D direction reduces (or decimates) the data rate from 12.288 Mb/s to 48 Kb/s. The decimation is distributed between the FIR filter and the IIR filter in the preferred embodiment, but may be carried more fully or entirely
either by the FIR filter or the IIR filter. In the disclosed embodiment, the FIR filter in each of the three digital filter/gain adjust modules 434, 436, 428 in the A/D direction decimates by 64, and the IIR filter in these digital filter/gain adjust
modules 434, 436, 428 decimates by 4. In the D/A direction, the FIR and IIR filters interpolate by 64 and 4, respectively. Therefore, the data rate output from the FIR filter is, e.g., 192 Kb/s, and the data rate output from the IIR filter is, e.g., 48
Kb/s, which is the final data rate of the AC link 406 (FIG. 3). Of course, decimation and interpolation may be performed between data rates other than to 48 Kb/s if full conformance with the AC link of the AC '97 specification is not desired.
The FIR and IIR filters are implemented in hardware in the disclosed embodiment, e.g., in a field programmable gate array (FPGA). Alternatively, the functions of the FIR and IIR filters may be performed in a processor such as a digital signal
processor (DSP). The FIR and IIR filtering and other details of conventional digital filter/gain adjuster modules are disclosed in more detail in U.S. Pat. No. 5,457,456, entitled "A Data Converter with Programmable Decimation of Interpolation", the
content of which is explicitly incorporated herein by reference.
The digital-to-digital .SIGMA./.DELTA. converters 456, 458, 460 receive, e.g., 20-bit .SIGMA./.DELTA. encoded data samples at, e.g., a 12.288 MHz data rate, and convert the same into 1-bit .SIGMA./.DELTA. encoded data samples at the same rate,
e.g., 12.288 Mb/s.
The digital .SIGMA./.DELTA. mixers 444, 446, 466, 468 are all identical in nature and provide completely asymmetrical mixing capabilities so that different audio signals may be mixed in the A/D direction (e.g., the record path) than that mixed
in the D/A direction (e.g., the playback path). As will be discussed in greater detail below, the digital .SIGMA./.DELTA. mixers 444, 446, 466, 468 each inventively contain overflow protection.
The digital filter/gain adjust modules 434, 436, 428, 450, 452 and 454 are shown in greater detail in FIGS. 5A(1), 5A(2) and 5B. FIG. 5A(1) depicts the signal flow of the filtering channels in the A/D (i.e., decimation) direction, while FIG.
5A(2) depicts the signal flow of the filtering channels in the D/A (i.e., interpolation) direction. FIG. 5B shows a more efficient utilization of hardware resources implemented in the disclosed embodiments wherein common circuitry is used for filtering
and gain control in both the A/D and D/A directions.
FIG. 5A(1) depicts each of the individual filter and gain adjust channels 434, 436 and 428 in the A/D direction, while FIG. 5A(2) depicts each of the individual filter and gain adjust channels 450, 452 and 454 in the D/A direction.
In FIG. 5A(1), data from an A/D converter, e.g., 12.288 Mb/s 1-bit .SIGMA./.DELTA. encoded data samples, is input to an FIR filter 502a operating as a decimator. The FIR filter 502a decimates the A/D signal from 1-bit .SIGMA./.DELTA. encoded
data samples at 12.288 Mb/s to 18-bit linear data samples at 192 Kb/s. The 18-bit linear data samples are output at 192 Kb/s from the FIR filter 502a and input to a gain/overflow module 506a, which provides gain and inventively checks to determine and
provide correction for overflow in the digital samples, as will be discussed in greater detail herein below. The digital gain/overflow module 506a allows, e.g., the insertion of 0, -6, -12 or -18 dB gain (i.e., attenuation).
The gain/overflow module outputs data samples, e.g., at 192 Kb/s to an IIR filter 508a, which is operated in a decimating mode for samples in the A/D direction. The IIR filter 508a decimates, e.g., the 20-bit linear data samples at 192 Kb/s by 4
to provide 20-bit linear data samples at 48 Kb/s. The IIR filter has a gain of 4 in the A/D direction, and a gain of 0.8 in the D/A direction.
FIG. 5A(2) shows the process flow in the D/A (i.e., interpolation) direction. In this direction, in the disclosed embodiment, 20-bit linear data samples are output at, e.g., 48 Kb/s from a sample source, e.g., the digital interface 352, and
provided to a gain/overflow module 506b. The gain/overflow module 506b provides gain and checks against overflow, as provided by the gain/overflow module 506a in the A/D direction.
In the D/A direction, e.g., 20-bit 48 Kb/s data samples are interpolated by 4 in the IIR filter 508b. Accordingly, 20-bit linear data samples are output from the IIR filter 508b at 192 Kb/s and directed to an FIR filter 502b. The FIR filter
502b interpolates, e.g., the 20-bit samples from 192 Kb/s to 12.288 Mb/s for output toward a D/A converter.
For ease of design, common circuitry in the filter channels in either the A/D (i.e. decimation) direction or D/A (i.e. interpolation) direction may be commonly utilized. For instance, samples in the A/D direction may be multiplexed with samples
in the D/A direction, and appropriately processed within common filtering components. The common filtering components include appropriate control signaling to indicate the direction of the current samples, e.g., the A/D direction or D/A direction.
In particular, FIG. 5B shows a digital filter channel capable of operation in either an A/D direction or a D/A direction. Control of the processing is multiplexed between interpolation and decimation, with appropriate latching of samples and
switching of multiplexing functions 504, 510 as necessary.
In FIG. 5B, a multiplexer function (MUX) 504 alternately selects for output either an A/D direction sample from the FIR filter 502 operating as a decimator, or a D/A direction sample from, e.g., the digital interface 352. Thus, since the
disclosed embodiment includes an equal number of filtering channels in both the A/D and D/A directions, every other sample output from the MUX 504 is a 18-bit, 192 Kb/s data sample from the FIR filter 502, and the alternating every other sample output
from the MUX 504 is a 20-bit, 48 Kb/s sample from the digital interface 352. The MUX 504 samples alternately between the A/D and D/A directions because of the symmetry provided by three filter channels in each direction in the present embodiment of an
audio codec. However, the particular number of decimation channels and the particular number of interpolation channels may be altered in accordance with the principles of the present invention.
The disclosed embodiment includes an IIR filter 508 to accomplish high out-of-band rejection, e.g., greater than about -74 dB of rejection. The FIR filters 502, 510 in the disclosed embodiment are implemented as comb filters because of ease of
design.
All or most of the decimation or interpolation performed in each digital filter/gain adjustment module 434, 436, 428, 450, 452 and 454 may be performed in either the FIR filter 502, 510 or the IIIR filter 508. Moreover, while the FIR filters
502, 510 in the disclosed embodiments are comb filters, other filter types may be implemented within the principles of the present invention.
FIG. 6A shows a conventional non-recursive comb filter, while FIG. 6B shows a recursive comb filter of the FIR filters 502, 510 of the present invention in greater detail.
In the non-recursive comb filter shown in FIG. 6A, separate taps 650-656 and summer 658 which sums the output from each of the separate taps 650-656 perform the comb filtering function. The separate taps 650-656 present little if any problem of
DC offset buildup because the internal nodes feed only forward, and any DC buildup would bleed off. However, the conventional non-recursive comb filter as shown in FIG. 6A is nevertheless disadvantageous because of the use of separate, non-recursive
taps 650-656. The separate taps 650-656 require a significant amount of space to implement in an integrated circuit.
In FIG. 6B, a recursive comb filter is implemented to reduce the required amount of space of the comb filter. The recursive comb filter is commonly referred to as a SINC.sup.3 filter, and has a pole on the unit circle. The comb filter of the
disclosed embodiment implements the following SINC.sup.3 function: ##EQU1## wherein N is the decimation or interpolation rate. A SINC.sup.3 filter is a common way of referring to a comb filter with a transfer function which has zeroes at the decimation
(or interpolation) rate so that every 192 KHz, the attenuation of the transfer function becomes infinity.
While a conventional comb or SINC.sup.3 filter may be implemented, conventional SINC.sup.3 filters are disadvantageous in that if any discontinuity in the input data is present, i.e., if the input data becomes unsynchronized, a DC value builds up
inside the filter and does not leak off. Unfortunately, this DC buildup eventually causes the filter to overload. The inventive SINC.sup.3 filter shown in FIG. 6B prevents DC buildup by resetting if the comb filter control signals are unstable, i.e.,
not synchronous, or if an overflow has occurred in the SINC.sup.3 filter. If either condition is true, the SINC.sup.3 filter is caused to reset to avoid a DC buildup.
Asynchronous conditions do not generally occur within the same integrated circuit because of the proximity and predictability of the elements. However, asynchronous conditions are possible when separate integrated circuits are interfaced
together, e.g., the AC controller 402 and the AC analog 404 of a conventional audio codec (FIG. 1). For instance, in the split-architecture audio codec, a frame signal is generated in the AC controller and AC link, which is transmitted to the AC analog
for generation of a lower speed clock. The externally generated frame signal may contain noise or jitter causing asynchronous operation of the comb filter.
The inventive SINC.sup.3 filter shown in FIG. 6B is implemented in two stages: one stage 602 is recursive operating under the control of a high speed oversampling clock CK1 (e.g., a 12.288 Mb/s clock), and another stage 604 operates under the
control of a lower speed clock CK2 (e.g., a 192 Kb/s clock). The decimation or interpolation rate N is equal to CK1/CK2. The stages 602, 604 shown in FIG. 6B are repeated three times to provide a SINC.sup.3 filter forming the FIR filters 502, 510 in an
embodiment of the present invention.
A decimating SINC.sup.3 is shown in FIG. 6B, while an interpolating SINC.sup.3 filter has the stages 602, 604 reversed from that shown in FIG. 6B.
The recursive stage 602 of the SINC.sup.3 filter is comprised of an adder circuit 620, and an output latch 622 to latch the output of the adder circuit 620 on the transition of the higher speed clock CK1. The output stage 604 of the SINC.sup.3
filter is comprised of an input latch 624 to latch a first input to a subtractor 628, and a second latch to latch the output of the first input latch 624 for input to the other input of the subtractor 628. The output of the subtractor 628 is latched in
a latch 630, for output to the overflow detector 608.
The recursive stage 602 operating under the control of the higher speed clock CK1 implements the transfer function 1/(1-Z.sup.-1), while the output stage 604 operating under the control of the lower speed clock CK2 implements the transfer
function (1-Z.sup.-N). When the stages 602 and 604 are placed in series as shown in FIG. 6B, the desired SINC.sup.3 transfer function results.
In order for the SINC.sup.3 filter to properly track the input signal, the recursive stage 602 must not operate for more than N cycles without a pulse of the lower speed clock CK2. A problem occurs when the system synchronization signal (e.g., a
framing signal) is noisy, jittery or otherwise occurs asynchronously. This condition may otherwise cause erroneous resetting of the control logic signals too early or too late. When this happens, the lower speed clock CK2 may not be generated during
the next frame, allowing the recursive stage 602 of the SINC.sup.3 | | |
