Multiplication method and multiplication circuit

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multiplication method and a multiplication circuit for executing fixed point multiplication instructions used for digital signal processing in image and sound processing fields.

2. Prior Art

FIG. 9 is a conceptual view showing a multiplication method in a multiplication instruction provided with a conventional rounding function.

This conventional multiplication method is carried out as described below. After a multiplication result 903 obtained by the multiplication of a multiplier 901 and a multiplicand 902 is rounded by adding 1 as a rounding signal 906 at a predetermined rounding position 905 where rounding is executed, a bit range 908 up to the rounding position 905 is discarded. The result thus obtained is taken as a multiplication result 907 subjected to rounding.

In the conventional example shown in FIG. 9, however, when multiplication requiring rounding is executed, 1 is added at the predetermined position 905 without exception regardless of how the multiplication result 907 is used in a subsequent process. In this case, the bit range 908 up to the predetermined rounding position 905 becomes meaningless as a multiplication result. When it is assumed that the m-th bit from the least significant bit of the multiplication result 903 is the predetermined rounding position, a bit range capable of being cut out as the multiplication result 907 subjected to rounding is limited to a high-order bit portion having its least significant bit at the (m+1)th bit from the least significant bit of the multiplication result 903.

Therefore, when the decimal point positions of a multiplier and a multiplicand are changeable for example, and when only the integer bits are desired to be cut out after the fraction portion of the multiplication result obtained by the multiplication of the multiplier and the multiplicand is rounded, the decimal point position of the multiplication result obtained by the multiplication changes depending on the decimal point positions of the multiplier and the multiplicand. For this reason, the user trying to execute a multiplication instruction must execute a shift operation for the multiplier or the multiplicand beforehand so that the predetermined rounding position 905 is located at a position suited for rounding the fraction portion (refer to Japanese Laid-open Patent Application No. 5-224888, for example). Alternatively, the user must execute multiplication first without rounding, and then round the fraction portion of the multiplication result.

As described above, in the conventional multiplication method, the user trying to execute a multiplication instruction must shift the multiplier or the multiplicand beforehand so that the predetermined rounding position 905 is located at a suitable rounding position in order that the multiplication result 907 subjected to rounding has a bit range desired to be cut out. Alternatively, the user must execute multiplication first without rounding, and then execute rounding by addition or the like depending on the bit range desired to be cut out from the multiplication result. This causes a problem of increasing the amount of processing.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a multiplication method and a multiplication circuit capable of attaining a rounding process at a suitable rounding position desired by the user without increasing the amount of processing in a process using a multiplication result subjected to rounding.

The multiplication method of the present invention comprises a multiplication process for multiplying a multiplicand by a multiplier, both obtained by a multiplication instruction, a rounding signal generation process for generating a rounding signal including a rounding value to be added to a low-order bit adjacent to the least significant bit in a given cut-out bit range of a multiplication result obtained by the multiplication process on the basis of a shift bit count signal corresponding to the difference between the least significant bit in the given cut-out bit range of the multiplication result obtained by the multiplication process and the least significant bit in a reference cut-out bit range, an addition process for adding the multiplication result obtained by the multiplication process to the rounding signal in order to generate a multiplication result obtained after rounding, and a shift process for shifting the multiplication result obtained after rounding by a shift bit count indicated by the shift bit count signal in order to cut out the given cut-out bit range from the multiplication result obtained after rounding.

With this multiplication method, by rounding the multiplication result obtained after rounding by using the rounding signal generated on the shift bit count signal corresponding to the shift bit count, the bit range to be cut out does not include any meaningless bits as a multiplication result. For a process using the multiplication result subjected to rounding, rounding can be executed at an appropriate rounding position desired by the user. Furthermore, unlike the conventional method, it is not necessary to shift the multiplier or multiplicand beforehand, and it is not necessary to execute rounding depending on the bit range desired to be cut out from the multiplication result after the multiplication is executed without rounding, thereby preventing the amount of processing from increasing. The result obtained by shifting and cutting out the multiplication result obtained after rounding generated by the addition process is referred to as a multiplication result subjected to rounding.

Furthermore, the multiplication method of the present invention, for carrying out a multiplication process by generating and adding subproducts, comprises a rounding signal generation process for generating a rounding signal including a rounding value to be added to a low-order bit adjacent to the least significant bit in a given cut-out bit range of a multiplication result obtained by the multiplication process on the basis of a shift bit count signal corresponding to the difference between the least significant bit in the given cut-out bit range of the multiplication result obtained by the multiplication process and the least significant bit in the reference cut-out bit range, a subproduct generation process for generating subproducts of a multiplier and a multiplicand obtained by a multiplication instruction, an addition process for adding all the subproducts generated by the subproduct generation process to the rounding signal in order to generate a multiplication result obtained after rounding, and a shift process for shifting the multiplication result obtained after rounding by a shift bit count indicated by the shift bit count signal in order to cut out the given cut-out bit range from the multiplication result obtained after rounding.

With this multiplication method, by rounding the multiplication result obtained after rounding by using the rounding signal generated on the shift bit count signal corresponding to the shift bit count, the bit range to be cut out does not include any meaningless bits as a multiplication result. For a process using the multiplication result subjected to rounding, rounding can be executed at an appropriate rounding position desired by the user. Furthermore, unlike the conventional method, it is not necessary to shift the multiplier or multiplicand beforehand, and it is not necessary to execute rounding depending on the bit range desired to be cut out from the multiplication result after the multiplication is executed without rounding, thereby preventing the amount of processing from increasing. In addition, by including the rounding process in the multiplication process comprising the subproduct generation process and the addition process, high-speed processing can be attained, and the size of the processing circuit can be made smaller.

Furthermore, the shift bit count signal may be used for the rounding signal generation process and the shift process after retained temporarily. With this method, the shift bit count signal can be set before the issue of the multiplication instruction by using a different instruction. It is not necessary to set the shift bit count signal by using the multiplication instruction. This prevents the length of the instruction code from increasing.

Furthermore, the shift bit count signal retained temporarily or a zero signal indicating a zero bit is selected for use in the rounding signal generation process and the shift process, and the zero signal is selected, the rounding signal generation process generates a rounding signal including a rounding value to be added to a low-order bit adjacent to the least significant bit in the reference cut-out bit range of the multiplication result obtained by the multiplication process, and the shift process carries out no shift on the multiplication result obtained after rounding. Therefore, when the zero signal is selected and used, it is possible to use the conventional multiplication method, wherein rounding is carried out at a predetermined fixed position, and no shift is carried out.

The multiplication circuit of the present invention comprises a multiplication means for inputting a multiplier and a multiplicand obtained by a multiplication instruction, and for outputting the multiplication result thereof, a rounding signal generation means for generating a rounding signal including a rounding value to be added to a low-order bit adjacent to the least significant bit in a given cut-out bit range of the multiplication result obtained by the multiplication means on the basis of a shift bit count signal corresponding to the difference between the least significant bit in the given cut-out bit range of the multiplication result obtained by the multiplication means and the least significant bit in the reference cut-out bit range, an addition means for adding the multiplication result obtained by the multiplication means to the rounding signal generated by the rounding signal generation means in order to generate a multiplication result obtained after rounding, and a shift means for shifting the multiplication result obtained after rounding generated by the addition means by a shift bit count indicated by the shift bit count signal in order to cut out the given cut-out bit range from the multiplication result obtained after rounding.

With this configuration, by rounding the multiplication result obtained after rounding by using the rounding signal generated on the shift bit count signal corresponding to the shift bit count, the bit range to be cut out does not include any meaningless bits as a multiplication result. For a process using the multiplication result subjected to rounding, rounding can be executed at an appropriate rounding position desired by the user. Furthermore, unlike the conventional method, it is not necessary to shift the multiplier or multiplicand beforehand, and it is not necessary to execute rounding depending on the bit range desired to be cut out from the multiplication result after the multiplication is executed without rounding, thereby preventing the amount of processing from increasing.

Furthermore, the multiplication circuit of the present invention, for carrying out a multiplication process by generating and adding subproducts, comprises a rounding signal generation means for generating a rounding signal including a rounding value to be added to a low-order bit adjacent to the least significant bit in a given cut-out bit range of a multiplication result obtained by the multiplication process on the basis of a shift bit count signal corresponding to the difference between the least significant bit in the given cut-out bit range of the multiplication result obtained by the multiplication process and the least significant bit in the reference cut-out bit range, a subproduct generation means for generating subproducts of a multiplier and a multiplicand obtained by a multiplication instruction, an addition means for adding all the subproducts generated by the subproduct generation means to the rounding signal generated by the rounding signal generation means in order to generate a multiplication result obtained after rounding, and a shift means for shifting the multiplication result obtained after rounding generated by the addition means by a shift bit count indicated by the shift bit count signal in order to cut out the given cut-out bit range from the multiplication result obtained after rounding.

With this configuration, by rounding the multiplication result obtained after rounding by using the rounding signal generated on the shift bit count signal corresponding to the shift bit count, the bit range to be cut out does not include any meaningless bits as a multiplication result. For a process using the multiplication result subjected to rounding, rounding can be executed at an appropriate rounding position desired by the user. Furthermore, unlike the conventional method, it is not necessary to shift the multiplier or multiplicand beforehand, and it is not necessary to execute rounding depending on the bit range desired to be cut out from the multiplication result after the multiplication is executed without rounding, thereby preventing the amount of processing from increasing. In addition, by including the rounding process in the multiplication process carried out by the subproduct generation means and the addition means, high-speed processing can be attained, and the size of the processing circuit can be made smaller.

Furthermore, a shift count retention means for temporarily retaining the shift bit count signal and for outputting the shift bit count signal to the rounding signal generation means and the shift means may be provided. With this configuration, the shift bit count signal can be set before the issue of the multiplication instruction by using a different instruction. It is not necessary to set the shift bit count signal by using the multiplication instruction. This prevents the length of the instruction code from increasing.

Furthermore, a shift count selection means for selecting the shift bit count signal of the shift count retention means or a zero signal indicating a zero bit and for outputting the selected signal to the rounding signal generation means and the shift means is provided between the shift count retention means and the rounding signal generation means, and when the shift count selection means selects and outputs the zero signal, the rounding signal generation means generates a rounding signal including a rounding value to be added to a low-order bit adjacent to the least significant bit in the reference cutout bit range of the multiplication result, and the shift means carries out no shift on the multiplication result obtained after rounding. Therefore, when the zero signal is selected and output, it is possible to use the conventional multiplication method, wherein rounding is carried out at a predetermined fixed position, and no shift is carried out.

Furthermore, a shift input switching means for selecting the output signal of the addition means or a different signal and for outputting the selected signal to the shift means may be provided between the addition means and the shift means. With this configuration, the different signal can be shifted only, without being multiplied.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing a multiplication circuit in accordance with a first embodiment of the present invention;

FIG 2 is a block diagram showing a multiplication circuit in accordance with a second embodiment of the present invention;

FIG. 3 is a block diagram showing a multiplication circuit in accordance with a third embodiment of the present invention;

FIG. 4 is a block diagram showing a multiplication circuit in accordance with a fourth embodiment of the present invention;

FIG. 5 is a block diagram showing a multiplication circuit in accordance with a fifth embodiment of the present invention;

FIG. 6 is a conceptual view showing a conventional multiplication method provided with an additional process for shifting a multiplication result;

FIG. 7 is a conceptual view showing a multiplication method in accordance with the present invention;

FIG. 8 is a conceptual view showing another multiplication method in accordance with the present invention;

FIG. 9 is a conceptual view showing a conventional multiplication method.

DESCRIPTION OF PREFERRED EMBODIMENTS

Multiplication methods and multiplication circuits for executing fixed point multiplication instructions used for digital signal processing in image and sound processing fields in accordance with embodiments of the present invention will be described below with reference to the accompanying drawings.

First Embodiment

FIG. 1 is a block diagram showing a multiplication circuit in accordance with a first embodiment of the present invention. Referring to FIG. 1, numeral 101 designates a multiplier, numeral 102 designates a multiplicand, numeral 103 designates a multiplication means, numeral 104 designates a multiplication result used as the output of the multiplication means 103, numeral 105 designates a rounding signal generation means, numeral 106 designates a rounding signal used as the output of the rounding signal generation means 105, numeral 107 designates an instruction control means of a processor, numeral 108 designates a shift bit count signal controlled by the instruction control means 107, numeral 109 designates an addition means, numeral 110 designates a multiplication result obtained after rounding as the output of the addition means 109, numeral 111 designates a register used as a means for storing the multiplication result 110 obtained after rounding, numeral 112 designates a barrel shifter used as a shift means, and numeral 113 designates a register used as a means for storing the output of the barrel shifter 112.

The multiplier 101 and the multiplicand 102 obtained by a multiplication instruction issued by the processor are input to the multiplication means 103, and the multiplication means 103 outputs the multiplication result 104. The shift bit count signal 108 output from the instruction control mean 107 is input to the rounding signal generation means 105, and the rounding signal generation means 105 generates the rounding signal 106. The multiplication result 104 and the rounding signal 106 are input to the addition means 109, and the addition means 109 outputs the multiplication result 110 obtained after rounding. The multiplication result 110 obtained after rounding is stored temporarily in the register 111 used as a multiplication result storage means. The output of the register 111 is input to the barrel shifter 112 used as a shift means, and the input signal is shifted depending on the shift bit count signal 108 output from the instruction control means 107. The output of the barrel shifter 112 is stored in the register 113 used as a means for storing the shift output.

With this configuration, when a multiplication instruction is issued, the multiplication of the multiplier 101 and the multiplicand 102 is executed by the multiplication means 103, and the multiplication result 104 is obtained. At the same time, by receiving the shift bit count signal 108 output beforehand from the instruction control means 107, the rounding signal generation means 105 generates the rounding signal 106. By adding the multiplication result 104 to the rounding signal 106 by using the addition means 109, the multiplication result 110 obtained after rounding is obtained and stored in the multiplication result storage register 111, thereby ending the execution of the multiplication instruction.

When a shift instruction is issued next by using the multiplication result storage register 111, the multiplication result stored in the multiplication result storage register 111 is shifted by the barrel shifter 112. Since the shift count of the barrel shifter 112 is determined by the shift bit count signal 108 which was also issued by the instruction control means 107 when the multiplication instruction was issued, the multiplication result stored in the multiplication result storage register 111 is shifted by the shift count indicated by the shift bit count signal 108, and the shifted value is stored in the shift result storage register 113.

Multiplication methods carried out by the multiplication circuit in accordance with the present embodiment of the present invention will be described below referring to FIGS. 6 to 8. FIG. 6 is a conceptual view showing a conventional multiplication method provided with an additional process for shifting a multiplication result, shown for convenience of comparison with the present invention.

First, the multiplication method shown in FIG. 6 will be described below. Numeral 601 designates a multiplier, numeral 602 designates a multiplicand, numeral 603 designates a multiplication result, numeral 604 designates a bit range desired to be cut out from the multiplication result 603, numeral 605 is a predetermined rounding position where rounding is executed, numeral 606 designates a rounding signal, numeral 607 designates a multiplication result obtained after rounding, numeral 608 designates a bit range made meaningless as a multiplication result by rounding, numeral 609 designates a left shift of k bits taken as an example of a shift operation used to cut out a bit range, and numeral 610 designates a shift result output after the shift operation.

When it is assumed that the rounding position 605 for the multiplication result 603 is located at the mth bit from least significant bit, the multiplication result 607 obtained after rounding is not subjected to a shift operation, that is, the multiplication result 607 obtained after rounding is subjected to a shift of 0 bits, and then output, after 1 is added to the mth bit from least significant bit as a rounding process. In this case, the output, that is, the shift result output 610, is assumed to be a high-order bit portion having its least significant bit at the (m+1) th bit from the least significant bit of the multiplication result 607.

When a bit range desired by the user is cut out from the multiplication result 603 by using a shift process, that is, when the range indicated by the bit range 604 is cut out for example in this case, a rounding process is executed at the predetermined rounding position 605 without exception if the rounding process of the conventional multiplication method is used. As a result, the desired shift result output 610 cut out by the left shift 609 of k bits includes meaningless bits as a multiplication result. For this reason, when the range indicated by the bit range 604 is desired to be cut out by using the conventional multiplication method, the range is cut out by discarding, without executing rounding. In this case, a large operation error occurs because of nonexecution of rounding, or rounding must be executed by a different process, thereby increasing process cycles.

In comparison with the conventional method, the multiplication methods shown in FIGS. 7 and 8 will be described below.

Referring to FIG. 7, numeral 701 designates a multiplier, numeral 702 designates a multiplicand, numeral 703 designates a multiplication result, numeral 704 designates a bit range desired to be cut out from the multiplication result 703, numeral 705 is a rounding position where rounding is executed, numeral 706 designates a rounding signal, numeral 707 designates a multiplication result obtained after rounding, numeral 708 designates a bit range made meaningless as a multiplication result by rounding, numeral 709 designates a left shift of k bits taken as an example of a shift operation for cutting out a bit range, numeral 710 is a shift result output after the shift operation, and numeral 711 designates the same predetermined rounding position as the predetermined rounding position 605 in the conventional method shown in FIG. 6.

In a manner similar to that of the conventional method, when it is assumed that the predetermined rounding position 711 for the multiplication result 703 is located at the mth bit from the least significant bit, the multiplication result 707 obtained after rounding is not subjected to a shift operation, that is, the multiplicatio