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Parallel access virtual channel memory system with cacheable channels    
United States Patent6167486   
Link to this pagehttp://www.wikipatents.com/6167486.html
Inventor(s)Lee; Jeffery H. (Sunnyvale, CA), Ando; Manabu (Los Gatos, CA)
AbstractA memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.
   














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Inventor     Lee; Jeffery H. (Sunnyvale, CA) , Ando; Manabu (Los Gatos, CA)
Owner/Assignee     NEC Electronics, Inc. (Santa Clara, CA)
Patent assignment
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Publication Date     December 26, 2000
Application Number     08/746,829
PAIR File History     Application Data   Transaction History
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Litigation
Filing Date     November 18, 1996
US Classification     711/120 711/123 711/150
Int'l Classification    
Examiner     Peikari; B. James
Assistant Examiner    
Attorney/Law Firm     MacPherson; Alan H. Skjerven, Morril, MacPherson, Franklin & Friel LLP Edwards; Gary J.
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Priority Data    
USPTO Field of Search     711/119 711/5 711/120 711/123 711/125 711/126 711/128 711/137 711/138 711/145 711/203 711/204 711/106 711/148 711/149 711/150 365/203 365/222 340/825.06 395/855
Patent Tags     parallel access virtual channel memory cacheable channels
   
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