Semiconductor devices having interconnections using standardized bonding locations and methods of designing

Claims

What is claimed is:

1. A semiconductor device, comprising:

a carrier substrate including a plurality of conductors on a surface thereof, the conductors of the plurality being arranged to mate with an array of external connections of a pitch and pattern and located over and projecting from an active surface of a first die;

a second die having an active surface with a plurality of bond pads arranged thereover in an arrangement at least partially different from the arrangement of the plurality of conductors on the surface of the carrier substrate;

a plurality of external connections on the second die located over and projecting from an active surface thereof, at least some of the plurality of external connections on the secind die being offset from at least some of the plurality of bond pads thereof, said plurality of external connections arranged in an array over the active surface of the second die, the array of external connections of the second die being arranged to substantially correspond in pitch and pattern to the pitch and pattern of the external connections of the array located over the active surface of the first die, the plurality of external connections of the second die being in mating contact with the conductors of the plurality on the surface of the carrier substrate; and

a plurality of circuit traces extending over the active surface of the second die and connecting at least some of the plurality of external connections on the second die to at least some of the plurality of bond pads on the second die;

wherein the second die differs from the first die in at least one of the following respects: size, shape, bond pad arrangement and circuitry.

2. The semiconductor device of claim 1, wherein at least a portion of at least one of said plurality of circuit traces is disposed on a discrete layer of dielectric material residing on said active surface of said second die.

3. The semiconductor device of claim 2, wherein said dielectric material is selected from the group comprising a polyimide, a siloxane polyimide and a spin-on glass.

4. The semiconductor device of claim 1, wherein at least a portion of at least one of said plurality of circuit traces is covered by a dielectric material.

5. The semiconductor device of claim 4, wherein said dielectric material is selected from the group comprising a polyimide, a siloxane polyimide and a spin-on glass.

6. The semiconductor device of claim 1, wherein said external connection arrays of said first die and said second die comprise arrays of conductive bumps.

7. The semiconductor device of claim 6, wherein said bumps are of a material selected from the group comprising a reflowable metal material, a conductive polymer and a polymer carrying conductive material.

8. The semiconductor device of claim 6, wherein said external connection arrays of said first die and said second die each comprise a BGA.

9. The semiconductor device of claim 1, wherein said second die is reduced in size in at least one dimension in comparison to said first die.

10. The semiconductor device of claim 9, wherein said second die is a shrink of said first die.

11. The semiconductor device of claim 1, wherein said external arrays of connections of said arrays of said first die and said second die are arranged in a single row on a center line.

12. The semiconductor device of claim 1, wherein said external connections of said arrays of said first die and said second die are arranged in at least two rows.

13. The semiconductor device of claim 1, wherein said external connections of said arrays of said first die and said second die are arranged in a rectangular configuration comprising at least one rectangle of connections.

14. The semiconductor device of claim 1, wherein said external connections of said arrays of said first die and said second die are arranged in rows and columns.

15. The semiconductor device of claim 1, wherein said external connection array of each of said first die and said second die comprises a circular array including at least one circle of connections.

16. A process of manufacturing a semiconductor device, comprising:

fabricating a die having an active surface with a plurality of bond pads arranged on said die and over said active surface, wherein said fabricating said die includes shrinking another die which is larger in at least one external dimension than said die, said another die carrying an external connection array projecting from an active surface thereof;

extending a plurality of circuit traces on said die and over said active surface of said die from at least some of said bond pads of said plurality to remote locations over said active surface and offset from said at least some of said bond pads of said plurality; and

forming external connections projecting from said active surface of said die, at least some of said external connections of said die being disposed at said remote locations whereby said external connections of said die define an array of external connections of the same pattern and pitch as said external connection array projecting from said active surface of said another die.

17. The process of claim 16, further including covering at least a portion of at least one of said plurality of circuit traces with a layer of dielectric material.

18. The process of claim 16, further including forming at least a portion of at least one of said plurality of circuit traces over a layer of dielectric material applied to said active surface.

19. The process of claim 16, further including forming said external connections as conductive bumps.

20. The process of claim 19, wherein said external connections are formed of a material selected from the group comprising a metal, a conductive polymer, and a polymer carrying conductive material.

21. The process of claim 16, further including providing a substrate bearing conductors thereon having contact areas in a pattern matching said external connection array and connecting said die by said external connections of said array to at least some of said substrate conductor contact areas.

22. A method of designing a die-adaptable semiconductor device assembly, comprising:

identifying at least one integrated circuit function to be fabricated on an active surface of a semiconductor die;

identifying a number of external connections for electrically communicating said at least one integrated circuit function to external circuitry;

selecting an external connection array of a given configuration and pitch of connections for effecting said electrical communication between said active surface of a semiconductor die including said at least one integrated circuit function and said external circuitry; and

positioning a different, selected external connection array having said given configuration and pitch of connections on the active surface of each of at least two semiconductor dies to enable said electrical communication by each of said at least two semiconductor dies directly to said external circuitry through said external connection array, said at least two semiconductor dies differing in at least one of the following respects: size, shape, and bond pad arrangement, and each of said at least two semiconductor dies including said at least one identified integrated circuit function.

23. The method of claim 22, further comprising providing said at least two semiconductor dies in the form of a first die and a second die which comprises a shrink of said first die.

24. The method of claim 22, further comprising providing said at least two semiconductor dies in the form of first and second dies of different manufacturing origin.

25. The method of claim 22, further including configuring circuit traces on at least one of said at least two semiconductor dies extending between locations of said external connections of said external connection array on said at least one semiconductor die and at least some bond pad locations on the active surface of the same semiconductor die.

26. The method of claim 25, wherein said at least some bond pad locations are located peripherally on said active surface of said at least one of said at least two semiconductor dies, and further comprising locating said external connection array relatively centrally on said active surfaces of said at least two semiconductor dies.

27. The method of claim 22, further comprising providing said at least two semiconductor dies in the form of at least a first die and at least one shrink of said first die, and further including selecting a pattern of circuit traces whereby at least some of said circuit traces extend from at least some bond pad locations on said first die to at least some of said external connections and pass through at least some bond pad locations of said at least one shrink.

28. The method of claim 22, further comprising designing an external connection array adapter usable with at least one of said at least two semiconductor dies and carrying said selected external connection array thereon, said at least one of said at least two semiconductor dies including bond pads offset from locations of said selected external connection array, configuring said external connection array adapter for disposition on the active surface of said at least one of said at least two semiconductor dies and including circuit traces communicating between bond pad locations of said at least one of said at least two semiconductor dies and external connections of said selected external connection array on said external connection array adapter, said positioning of said external connection array on said at least one of said at least two semiconductor dies comprising applying said external connection array adapter to the active surface thereof with at least some bond pads of said at least one of said at least two semiconductor die in communication with at least some of said different, selected circuit traces.

29. A semiconductor device, comprising:

a plurality of external connections arranged in an array selected for disposition over, and to project from, an active surface of each of a first die and a second die, the second die differing from the first die in at least one of the following respects: size, shape, bond pad arrangement and circuitry, wherein the array of external connections is of a pitch and pattern suitable for mating with conductors carried on a surface of a substrate;

wherein each die of the first die and the second die carries external connections arranged in the array on an active surface thereof, at least one die of the first die and the second die includes a plurality of bond pads over an active surface thereof including integrated circuitry, at least some of the plurality of bond pads are located on the at least one die laterally offset from at least some external connection locations of the array carried thereon and a plurality of circuit traces extend over the active surface of the at least one die and connect the at least some of the plurality of bond pads on the at least one die to the at least some external connections of the array carried on the at least one die from which the at least some of the plurality of bond pads of the at least one die are laterally offset.

30. The semiconductor device of claim 29, wherein the plurality of circuit traces is formed on the at least one die.

31. The semiconductor device of claim 29, wherein the plurality of circuit traces is preformed on a dielectric carrier applied to said active surface of the at least one die.

32. The semiconductor device of claim 29, wherein the plurality of traces is at least partially covered by a dielectric material.

33. The semiconductor device of claim 29, wherein the external connections comprise conductive bumps.

34. A method of reconfiguring die I/O patterns, comprising:

selecting a first die having an active surface bearing a first I/O pattern on an active surface thereof;

selecting a second die having an active surface bearing a second I/O pattern on an active surface thereof, said second I/O pattern being different from said first I/O pattern; and

reconfiguring at least one of said first and said second active surface I/O patterns on an active surface of at least one of said respective dies so that said first die and said second die present a common I/O pattern from their respective active surfaces.

35. The method of claim 34, wherein said common I/O pattern differs from both said first I/O patt