A method of locating faults occurred in an LSI (Large Scale Integrated Circuit) is disclosed. Block-by-block logic information each varying in accordance with a test vector are output by dump processing using logic simulation on the basis of circuit connection information. The block-by-block logic information varying in accordance with the test vector are combined with Iddq information showing whether or not an Iddq error has occurred test vector by test vector. These information are used to execute calculation with each block on a test vector basis. As a result, a block involving a fault is detected. Subsequently, a fault is located in the fault block on a transistor basis by use of logic information showing whether or not the Iddq error is present in the block.
A setting of a logical state in an integrated circuit is changed, a plurality of measurement patterns which are used in a quiescent power source current test of the integrated circuit are formed, an internal state value 0/1 of each net at the time when the measurement patterns are supplied by a simulation of the integrated circuit is derived, and further, a pass or fail test result is obtained every measurement pattern by the quiescent power source current test in which a plurality of measurement patterns were supplied to the integrated circuit determined to be a defective device. A state value variable in which the internal state values of all measurement patterns have been stored every net and a test result variable in which the pass or fail test result has been stored every measurement pattern are formed on the basis of those measurement patterns, internal state values, and test results. A combination of the state value variable of each net and the test result variable are compared between the nets, thereby discriminating a short-circuit failure position in the integrated circuit.
A method for improving the signal-to-noise ratio in an I.sub.DDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An I.sub.DDQ defect is activated to generate I.sub.DDQ defect current within the integrated circuit. An amount of I.sub.DDQ defect current generated within each area is measured at the terminals provided thereto. Based on the I.sub.DDQ current measurement on each area, an I.sub.DDQ current map is created. By analyzing the I.sub.DDQ current map, the presence and location of the defect is determined. Based on the determination, the I.sub.DDQ defect is isolated.
A method is presented for generating test vectors for an integrated circuit. Input test vectors and output test vectors are generated for non-core cell portions of the integrated circuit. Input test vectors and output test vectors are generated for core cell partitions of the integrated circuit. The input test vectors for the non-core cell portions and the input test vectors for the core cell partitions are combined into a single combined input test vector.
A systematic methodology to analyze a full scan dump is presented. The methodology is knowledge-based, i.e., the methodology intelligently processes a full scan dump using knowledge of the system from which the full scan is obtained.
A verifying method and apparatus verifies operation of a semiconductor circuit device by inputting, to a logical simulator, logical models representing a logic circuit and an analog circuit, adding, to the logical model representing the analog circuit, a function that generates a function value in accordance with the state of connections between terminals of the analog circuit and terminals of the logic circuit, outputting the result of comparing the function value generated by the function and an expected value, and, based on a result of the comparison, determining whether or not there is a connection error between the terminals of the analog circuit and the terminals of the logic circuit.
