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High temperature, conductive thin film diffusion barrier for ceramic/metal systems    
United States Patent6178082   
Link to this pagehttp://www.wikipatents.com/6178082.html
Inventor(s)Farooq; Mukta S. (Hopewell Junction, NY); Kotecki; David E. (Hopewell Junction, NY); Rita; Robert A. (Wappingers Falls, NY); Rossnagel; Stephen M. (Pleasantville, NY)
AbstractA multilayer ceramic substrate having a thin film structure containing capacitor connected thereto is provided as an interposer capacitor, the capacitor employing platinum as the bottom electrode of the capacitor. In a preferred capacitor, a dielectric material such as barium titanate is used as the dielectric material between the capacitor electrodes. The fabrication of the interposer capacitor requires an in-situ or post deposition high temperature anneal and the use of such dielectrics requires heating of the capacitor structure in a non-reducing atmosphere. A layer of a high temperature, thin film diffusion barrier such as TaSiN on the lower platinum electrode between the electrode and underlying multilayer ceramic substrate prevents or minimizes oxidization of the metallization of the multilayer ceramic substrate to which the thin film structure is connected during the fabrication process. A method is also provided for fabricating an interposer capacitor with a multilayer ceramic substrate base and a thin film multilayer structure having at least one capacitor comprising at least one bottom platinum electrode.
   














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Drawing from US Patent 6178082
High temperature, conductive thin film diffusion barrier for ceramic/metal

     systems - US Patent 6178082 Drawing
High temperature, conductive thin film diffusion barrier for ceramic/metal systems
Inventor     Farooq; Mukta S. (Hopewell Junction, NY); Kotecki; David E. (Hopewell Junction, NY); Rita; Robert A. (Wappingers Falls, NY); Rossnagel; Stephen M. (Pleasantville, NY)
Owner/Assignee     International Business Machines Corporation (Armonk, NY)
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Publication Date     January 23, 2001
Application Number     09/031,236
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     February 26, 1998
US Classification     361/303 257/E23.067 257/E23.072 257/E23.077 361/306.1 361/321.1 361/763
Int'l Classification     H01G 004/005
Examiner     Kincaid; Kristine
Assistant Examiner     Thomas; Eric
Attorney/Law Firm     LLC, Tomaszewski; John J. DeLio & Peterson Ahsan; Aziz M. ,
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USPTO Field of Search     361/306.1 361/306.3 361/306.2 361/301.1 361/301.2 361/301.4 361/303 361/305 361/309 361/321.1 361/2 361/3 361/4 361/5 361/6 361/7 361/8 361/9 361/10 361/11 361/12 361/13 361/14 361/15 361/16 361/17 361/18 361/19 361/20 361/21 361/22 361/23 361/24 361/25 361/26 361/27 361/28 361/29 361/30 361/31 361/32 361/33 361/34 361/35 361/36 361/37 361/38 361/39 361/40 361/41 361/42 361/43 361/44 361/45 361/46 361/47 361/48 361/49 361/50 361/51 361/52 361/53 361/54 361/55 361/56 361/57 361/58 361/59 361/60 361/61 361/62 361/63 361/64 361/65 361/66 361/67 361/68 361/69 361/70 361/71 361/72 361/73 361/74 361/75 361/76 361/77 361/78 361/79 361/80 361/81 361/82 361/83 361/84 361/85 361/86 361/87 361/88 361/89 361/90 361/91 361/92 361/93 361/94 361/95 361/96 361/97 361/98 361/99 361/100 361/101 361/102 361/103 361/104 361/105 361/106 361/107 361/108 361/109 361/110 361/111 361/112 361/113 361/114 361/115 361/116 361/117 361/118 361/119 361/120 361/121 361/122 361/123 361/124 361/125 361/126 361/127 361/128 361/129 361/130 361/131 361/132 361/133 361/134 361/135 361/136 361/137 361/138 361/139 361/140 361/141 361/142 361/143 361/144 361/145 361/146 361/147 361/148 361/149 361/150 361/151 361/152 361/153 361/154 361/155 361/156 361/157 361/158 361/159 361/160 361/161 361/162 361/163 361/164 361/165 361/166 361/167 361/168 361/169 361/170 361/171 361/172 361/173 361/174 361/175 361/176 361/177 361/178 361/179 361/180 361/181 361/182 361/183 361/184 361/185 361/186 361/187 361/188 361/189 361/190 361/191 361/192 361/193 361/194 361/195 361/196 361/197 361/198 361/199 361/200 361/201 361/202 361/203 361/204 361/205 361/206 361/207 361/208 361/209 361/210 361/211 361/212 361/213 361/214 361/215 361/216 361/217 361/218 361/219 361/220 361/221 361/222 361/223 361/224 361/225 361/226 361/227 361/228 361/229 361/230 361/231 361/232 361/233 361/234 361/235 361/236 361/237 361/238 361/239 361/240 361/241 361/242 361/243 361/244 361/245 361/246 361/247 361/248 361/249 361/250 361/251 361/252 361/253 361/254 361/255 361/256 361/257 361/258 361/259 361/260 361/261 361/262 361/263 361/264 361/265 361/266 361/267 361/268 361/269 361/270 361/271 361/272 361/273 361/274 361/275 361/276 361/277 361/278 361/279 361/280 361/281 361/282 361/283 361/284 361/285 361/286 361/287 361/288 361/289 361/290 361/291 361/292 361/293 361/294 361/295 361/296 361/297 361/298 361/299 361/300 361/301 361/302 361/303 361/304 361/305 361/306 361/307 361/308 361/309 361/310 361/311 361/312 361/313 361/314 361/315 361/316 361/317 361/318 361/319 361/320 361/321.5 361/763
Patent Tags     high temperature, conductive thin film diffusion barrier ceramic/metal
   
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ReferenceRelevancyCommentsReferenceRelevancyComments
5874369
Farooq
438/707
Feb,1999

[0 after 0 votes]
5854534
Beilin

Dec,1998

[0 after 0 votes]
5617290
Kulwicki

Apr,1997

[0 after 0 votes]
5504041
Summerfelt

Apr,1996

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5258236
Arjavalingam
428/626
Nov,1993

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5177670
Shinohara
361/738
Jan,1993

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5144526
Vu
361/321.1
Sep,1992

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5099388
Ogawa
361/321.2
Mar,1992

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5065275
Fujisaki

Nov,1991

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5043223
Kumagai
428/432
Aug,1991

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4954877
Nakanishi
257/659
Sep,1990

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4567542
Shimada
361/321.4
Jan,1986

[0 after 0 votes]
4407007
Desai
257/697
Sep,1983

[0 after 0 votes]
4349862
Bajorek
361/762
Sep,1982

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Thus, having described the invention, what is claimed is:

1. An interposer capacitor comprising:

a multilayer ceramic substrate comprising a plurality of ceramic layers having therein metallized circuitry, interconnecting metallized vias and bottom to top vias;

a thin film structure electrically connected to the multilayer ceramic substrate, the thin film structure containing at least one capacitor comprising at least one lower first electrode comprising a layer of first conductive material and an upper second electrode comprising a layer of second conductive material with a dielectric material therebetween with each electrode layer being connected by wiring to a corresponding pad on the surface of the thin film structure; and a barrier layer on the lower surface of the first conductive material, the barrier layer being between the first conductive material and the vias and metallized circuitry of the multilayer ceramic substrate.

2. The structure of claim 1 wherein the barrier layer comprises conductive materials, silicides or other low resistance inert materials.

3. The structure of claim 1 wherein the barrier layer is selected from the group consisting of tantalum silicon nitride, tantalum aluminum nitride, titanium silicon nitride, titanium nitride, tantalum nitride, tungsten nitride and titanium aluminum nitride.

4. The structure of claim 1 wherein the conductive materials are selected from the group consisting of platinum, iridium, ruthenium, palladium, gold, silver or alloys thereof or conductive oxides RuOx and IrOx.

5. The structure of claim 1 wherein the lower electrode comprises the layer of first conductive material and the barrier layer.

6. The structure of claim 1 wherein the dielectric material is selected from the group consisting of barium titanate, barium strontium titanate, strontium titanate, barium zirconate titanate, lead lanthanum zirconate titanate, lead zirconate titanate or tantalum oxide.

7. The Structure of claim 1 wherein the barrier layer is about 50 to 5000 .ANG. thick.

8. A multilayer electronic component comprising a lower electronic component and an upper electronic component which are electrically connected by the interposer capacitor of claim 1.

9. A method for fabricating an interposer capacitor comprising:

forming a thin film structure on the surface of a multilayer ceramic substrate having metallization therein, metal containing via interconnectings and bottom to top vias, the thin film structure containing at least one capacitor within said thin film structure comprising a first layer of conductive material as a lower first electrode, a dielectric material layer formed on the upper surface of the first electrode and an upper second layer of conductive material on the surface of the dielectric as a second electrode, the first electrode and second electrode being connected to corresponding pads on the surface of the thin film structure by separate wirings from each electrode, the lower first electrode having a barrier layer on the lower surface of the first electrode between the first electrode and the vias and metallization of the multilayer ceramic substrate.

10. The method of claim 9 wherein the barrier layer comprises conductive materials, silicides or other low resistance inert materials.

11. The method of claim 9 wherein the barrier layer is selected from the group consisting of tantalum silicon nitride, tantalum aluminum nitride, titanium silicon nitride, titanium nitride, tantalum nitride, tungsten nitride and titanium aluminum nitride.

12. The method of claim 9 wherein the conductive materials are selected from the group consisting of platinum, iridium, ruthenium, palladium, gold, silver or alloys thereof or conductive oxides RuOx and IrOx.

13. The method of claim 9, wherein the lower first electrode comprises the layer of first conductive material and the barrier layer.

14. The method of claim 8 wherein the dielectric material is selected from the group consisting of barium titanate, barium strontium titanate, strontium titanate, barium zirconate titanate, lead lanthanum zirconate titanate, lead zirconate titanate or tantalum oxide.

15. The method of claim 9 wherein the barrier layer is about 50 to 5000 .ANG. thick.
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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to multilayer electronic components and, in particular, to interposer thin film containing capacitors which use a noble metal such as platinum, iridium, palladium, ruthenium, silver, gold, etc. or alloys thereof as a capacitor electrode and to a diffusion barrier material (such as TaSiN, TiN, TaN, TiAlN, etc.) used in combination with the electrode to minimize circuitry oxidation and to provide an enhanced electronic component.

2. Description of Related Art

Multilayer substrates with capacitors have found wide spread use in electronics as integrated circuit packages. Electronic components are being made smaller in size with a higher circuit density and to meet these requirements it is necessary to use fabrication materials having enhanced properties such as increased conductivity, higher dielectric constant values, etc. Many of these materials however, do not have properties which enable their use with the other components of the multilayer substrate and accordingly, their use is limited in the fabrication of multilayer electronic components.

Ceramics have found widespread use in electronics as a substrate for integrated circuit packages including multilayer ceramic substrates having inner capacitors. In general, a metallized circuit pattern is applied to the ceramic substrate which is in the form of a greensheet, and the greensheet stacked with other metallized greensheets and the stack sintered to create a monolith of substrate and circuitry. Multilayer circuit packages are constructed by combining ceramic particles and organic binders into unfired or "greensheet" tape. Interlayer conductive pads, known as "vias", are then inserted (punched) through the layer, and the vias filled with metals (Mo, Cu, W, etc.) forming electronic interconnections between the circuits. Metallized circuit patterns are then applied to the punched greensheet as is well known in the art and the layers stacked and sintered.

A capacitor can be formed within the multilayer substrate by sandwiching an inner dielectric layer between a pair of electrodes. Conductive pads are formed on the top sheet and wirings are formed within the substrate to connect the capacitor electrodes to the pads. U.S. Pat. Nos. 4,567,542; 5,065,275; 5,099,388 and 5,144,526 show such multilayer ceramic (MLC) products having internal capacitors and the disclosure of these patents are hereby incorporated by reference.

A capacitor structure can alternately be formed by using thin films of electrodes and dielectrics which are deposited on a prefabricate