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| United States Patent | 6178082 |
| Link to this page | http://www.wikipatents.com/6178082.html |
| Inventor(s) | Farooq; Mukta S. (Hopewell Junction, NY);
Kotecki; David E. (Hopewell Junction, NY);
Rita; Robert A. (Wappingers Falls, NY);
Rossnagel; Stephen M. (Pleasantville, NY) |
| Abstract | A multilayer ceramic substrate having a thin film structure containing
capacitor connected thereto is provided as an interposer capacitor, the
capacitor employing platinum as the bottom electrode of the capacitor. In
a preferred capacitor, a dielectric material such as barium titanate is
used as the dielectric material between the capacitor electrodes. The
fabrication of the interposer capacitor requires an in-situ or post
deposition high temperature anneal and the use of such dielectrics
requires heating of the capacitor structure in a non-reducing atmosphere.
A layer of a high temperature, thin film diffusion barrier such as TaSiN
on the lower platinum electrode between the electrode and underlying
multilayer ceramic substrate prevents or minimizes oxidization of the
metallization of the multilayer ceramic substrate to which the thin film
structure is connected during the fabrication process. A method is also
provided for fabricating an interposer capacitor with a multilayer ceramic
substrate base and a thin film multilayer structure having at least one
capacitor comprising at least one bottom platinum electrode. |
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Title Information  |
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Drawing from US Patent 6178082 |
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High temperature, conductive thin film diffusion barrier for ceramic/metal
systems |
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| Publication Date |
January 23, 2001 |
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| Filing Date |
February 26, 1998 |
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Title Information  |
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References  |
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U.S. References |
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| | Reference | Relevancy | Comments | Reference | Relevancy | Comments | 5874369 Farooq 438/707 Feb,1999 |      Your vote accepted [0 after 0 votes] | | 5854534 Beilin
Dec,1998 |      Your vote accepted [0 after 0 votes] | | 5617290 Kulwicki
Apr,1997 |      Your vote accepted [0 after 0 votes] | | 5504041 Summerfelt
Apr,1996 |      Your vote accepted [0 after 0 votes] | | 5258236 Arjavalingam 428/626 Nov,1993 |      Your vote accepted [0 after 0 votes] | | 5177670 Shinohara 361/738 Jan,1993 |      Your vote accepted [0 after 0 votes] | | 5144526 Vu 361/321.1 Sep,1992 |      Your vote accepted [0 after 0 votes] | | 5099388 Ogawa 361/321.2 Mar,1992 |      Your vote accepted [0 after 0 votes] | | 5065275 Fujisaki
Nov,1991 |      Your vote accepted [0 after 0 votes] | | 5043223 Kumagai 428/432 Aug,1991 |      Your vote accepted [0 after 0 votes] | | 4954877 Nakanishi 257/659 Sep,1990 |      Your vote accepted [0 after 0 votes] | | 4567542 Shimada 361/321.4 Jan,1986 |      Your vote accepted [0 after 0 votes] | | 4407007 Desai 257/697 Sep,1983 |      Your vote accepted [0 after 0 votes] | | 4349862 Bajorek 361/762 Sep,1982 |      Your vote accepted [0 after 0 votes] | | |
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| Market Size |
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Market Review  |
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Technical Review  |
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Claims  |
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Thus, having described the invention, what is claimed is:
1. An interposer capacitor comprising:
a multilayer ceramic substrate comprising a plurality of ceramic layers
having therein metallized circuitry, interconnecting metallized vias and
bottom to top vias;
a thin film structure electrically connected to the multilayer ceramic
substrate, the thin film structure containing at least one capacitor
comprising at least one lower first electrode comprising a layer of first
conductive material and an upper second electrode comprising a layer of
second conductive material with a dielectric material therebetween with
each electrode layer being connected by wiring to a corresponding pad on
the surface of the thin film structure; and a barrier layer on the lower
surface of the first conductive material, the barrier layer being between
the first conductive material and the vias and metallized circuitry of the
multilayer ceramic substrate.
2. The structure of claim 1 wherein the barrier layer comprises conductive
materials, silicides or other low resistance inert materials.
3. The structure of claim 1 wherein the barrier layer is selected from the
group consisting of tantalum silicon nitride, tantalum aluminum nitride,
titanium silicon nitride, titanium nitride, tantalum nitride, tungsten
nitride and titanium aluminum nitride.
4. The structure of claim 1 wherein the conductive materials are selected
from the group consisting of platinum, iridium, ruthenium, palladium,
gold, silver or alloys thereof or conductive oxides RuOx and IrOx.
5. The structure of claim 1 wherein the lower electrode comprises the layer
of first conductive material and the barrier layer.
6. The structure of claim 1 wherein the dielectric material is selected
from the group consisting of barium titanate, barium strontium titanate,
strontium titanate, barium zirconate titanate, lead lanthanum zirconate
titanate, lead zirconate titanate or tantalum oxide.
7. The Structure of claim 1 wherein the barrier layer is about 50 to 5000
.ANG. thick.
8. A multilayer electronic component comprising a lower electronic
component and an upper electronic component which are electrically
connected by the interposer capacitor of claim 1.
9. A method for fabricating an interposer capacitor comprising:
forming a thin film structure on the surface of a multilayer ceramic
substrate having metallization therein, metal containing via
interconnectings and bottom to top vias, the thin film structure
containing at least one capacitor within said thin film structure
comprising a first layer of conductive material as a lower first
electrode, a dielectric material layer formed on the upper surface of the
first electrode and an upper second layer of conductive material on the
surface of the dielectric as a second electrode, the first electrode and
second electrode being connected to corresponding pads on the surface of
the thin film structure by separate wirings from each electrode, the lower
first electrode having a barrier layer on the lower surface of the first
electrode between the first electrode and the vias and metallization of
the multilayer ceramic substrate.
10. The method of claim 9 wherein the barrier layer comprises conductive
materials, silicides or other low resistance inert materials.
11. The method of claim 9 wherein the barrier layer is selected from the
group consisting of tantalum silicon nitride, tantalum aluminum nitride,
titanium silicon nitride, titanium nitride, tantalum nitride, tungsten
nitride and titanium aluminum nitride.
12. The method of claim 9 wherein the conductive materials are selected
from the group consisting of platinum, iridium, ruthenium, palladium,
gold, silver or alloys thereof or conductive oxides RuOx and IrOx.
13. The method of claim 9, wherein the lower first electrode comprises the
layer of first conductive material and the barrier layer.
14. The method of claim 8 wherein the dielectric material is selected from
the group consisting of barium titanate, barium strontium titanate,
strontium titanate, barium zirconate titanate, lead lanthanum zirconate
titanate, lead zirconate titanate or tantalum oxide.
15. The method of claim 9 wherein the barrier layer is about 50 to 5000
.ANG. thick. |
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Claims  |
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Description  |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to multilayer electronic components and, in
particular, to interposer thin film containing capacitors which use a
noble metal such as platinum, iridium, palladium, ruthenium, silver, gold,
etc. or alloys thereof as a capacitor electrode and to a diffusion barrier
material (such as TaSiN, TiN, TaN, TiAlN, etc.) used in combination with
the electrode to minimize circuitry oxidation and to provide an enhanced
electronic component.
2. Description of Related Art
Multilayer substrates with capacitors have found wide spread use in
electronics as integrated circuit packages. Electronic components are
being made smaller in size with a higher circuit density and to meet these
requirements it is necessary to use fabrication materials having enhanced
properties such as increased conductivity, higher dielectric constant
values, etc. Many of these materials however, do not have properties which
enable their use with the other components of the multilayer substrate and
accordingly, their use is limited in the fabrication of multilayer
electronic components.
Ceramics have found widespread use in electronics as a substrate for
integrated circuit packages including multilayer ceramic substrates having
inner capacitors. In general, a metallized circuit pattern is applied to
the ceramic substrate which is in the form of a greensheet, and the
greensheet stacked with other metallized greensheets and the stack
sintered to create a monolith of substrate and circuitry. Multilayer
circuit packages are constructed by combining ceramic particles and
organic binders into unfired or "greensheet" tape. Interlayer conductive
pads, known as "vias", are then inserted (punched) through the layer, and
the vias filled with metals (Mo, Cu, W, etc.) forming electronic
interconnections between the circuits. Metallized circuit patterns are
then applied to the punched greensheet as is well known in the art and the
layers stacked and sintered.
A capacitor can be formed within the multilayer substrate by sandwiching an
inner dielectric layer between a pair of electrodes. Conductive pads are
formed on the top sheet and wirings are formed within the substrate to
connect the capacitor electrodes to the pads. U.S. Pat. Nos. 4,567,542;
5,065,275; 5,099,388 and 5,144,526 show such multilayer ceramic (MLC)
products having internal capacitors and the disclosure of these patents
are hereby incorporated by reference.
A capacitor structure can alternately be formed by using thin films of
electrodes and dielectrics which are deposited on a prefabricate | | |