Digital signal processing assembly and test method

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A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of fabrication of printed circuit boards. More specifically, the present invention relates to the fabrication of modular printed circuit boards.

2. Description of the Related Art

In the past, both processors and memory circuits were mounted directly on a motherboard. This required the motherboard designer to include pin layout and trace patterns for each of these integrated circuits in the motherboard design. As a result, any change requiring a different processor or memory circuit required changing the motherboard.

One technique used to solve the problem of continuously redesigning the motherboard whenever a different memory circuit was needed was to move the memory to a separate, removable circuit board. The removable circuit board, in turn, connected to the motherboard. Another approach was to make custom printed circuit boards that contained both processors and memory. However, customized circuit boards do not permit easy interchangeability or upgrades. Further, the cost of creating custom printed circuit boards can be substantial.

There is also an ongoing need to decrease the size of printed circuit boards while at the same time increasing the number of processors and memory circuits hosted on the board.

SUMMARY OF THE INVENTION

The invention enhances the modularity of replaceable printed circuit boards which support processors and memories. The motherboard does not have to provide interconnections between the processors and the memories, and, as a result, can be less complicated and less expensive to manufacture.

Because the processors and associated memory circuits are provided to a system in a modular board, the layout and design for the specific integrated circuit used can be accomplished by a third party manufacturer of the modular board. The host motherboard only needs to be designed to interconnect with the pinouts of the modular board.

The modular design of the processors permits simpler upgrades and easy repairs. In contrast, if the processors are mounted directly on the motherboard, any upgrades or repairs would require replacing the entire motherboard, even if every other component on the motherboard remained the same. The present invention permits upgrades and repairs by simply replacing the printed circuit board module.

Modularity also provides increased performance. The impedance of signals travelling between processors and memories in a module may be matched to provide better performance. In contrast, it is more difficult to obtain impedance matching of signals on a motherboard due to the size and the number of components involved.

One embodiment of the invention decreases the amount of escape routing needed on a printed circuit through the use of microvias. A processor typically connects to the printed circuit board through a footprint, such as a ball grid array. With the use of microvias, individual surface mount pads may be directly connected to a lower layer of the printed circuit board without the use of escape routing. By decreasing the escape routing for each integrated circuit, the layout of the trace routing for the printed circuit board is simplified and the size of the printed circuit board may be decreased.

Another embodiment of the invention uses symmetry to improve the design of the processor module. Processor footprints and memory footprints are included on both the front and back side of the printed circuit board. The layouts of the front and back sides are similar such that the footprints of at least one integrated circuit on the front side is aligned with the footprint of a corresponding integrated circuit on the back side. The symmetrical design increases the number of integrated circuits that can be hosted on the printed circuit board and also permits the use of more drilled vias extending through the printed circuit board. Because the layouts are similar, a via drilled through a pad quadrant (the area between four surface mount pads) on the front side of the printed circuit board will exit the back side of the printed circuit board through a similar pad quadrant. This feature permits processors and memory integrated circuits to be mounted on both sides of the printed circuit board without a via drilled through one quadrant interfering with a surface mount pad on the opposite side.

Another embodiment of the invention also reduces crosstalk between signal layers through isolation. Printed circuit boards typically contain a ground layer. In one aspect of the invention, the ground layer is located between the top signal layer and a second signal layer. Because the two signal layers are separated by the ground layer, crosstalk is reduced. Because the printed circuit board is symmetrical, the bottom layers include a bottom signal layer and another signal layer separated by a second ground layer.

Another embodiment of the invention permits testing of the processors regardless of how many processors are mounted on the module. By linking the JTAG inputs and outputs of each processor footprint, a series testing circuit is created. If a processor is not mounted with a processor footprint, a testing bypass device is added to permit the test signal to pass.

Another embodiment of the invention is a method of testing integrated circuits mounted on a printed circuit board including linking a plurality of footprints to create a test path. The test path has an input and an output, and each of the footprints has a test input and a test output. The method further comprises the steps of inserting a test bypass element between the test input and the test output of any footprint not populated by an integrated circuit and then applying a test vector to the test input pin of the test path.

Another embodiment of the invention is a multilayer printed circuit board comprising a first signal layer having a first plurality of signal lines and a second signal layer having a second plurality of signal lines. A signal may travel from one of the first plurality of signal lines to one of the second plurality of signal lines without encountering a substantial change in impedance. A ground layer is located between the signal layers to reduce crosstalk between the signal layers.

Another embodiment of the invention is a printed circuit board having at least twelve footprints capable of mounting integrated circuits. The printed circuit board comprises a plurality of conductive layers and a plurality of insulation layers. The conductive layers are separated by the insulation layers. The layers have a dimension of approximately 11.43 centimeters in length and approximately 2.5 centimeters in height. Surface mount pads are located within the footprints and are adapted to mount half of the integrated circuits on a first conductive layer, or top signal layer of the printed circuit board. Other surface mount pads are located within the footprints and are adapted to mount half of the integrated circuits on a second conductive layer, or bottom signal layer of the printed circuit board. A plurality of microvias within each surface mount pad directly electrically connects either the top signal layer to a first ground layer or the bottom signal layer to a second ground layer.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features and advantages of the invention will become more apparent upon reading the following detailed description and upon reference to the accompanying drawings.

FIG. 1 illustrates a routing device including printed circuit boards having replaceable modules according to the present invention.

FIG. 2 is a plan view of a printed circuit board including modules according to the present invention.

FIG. 3A is a plan view of the top surface of a module according to the present invention.

FIG. 3B is a plan view of the bottom surface of a module according to the present invention.

FIG. 4 is an edge view illustrating the layers in a module according to the present invention.

FIG. 5A is a