Method and system for automatic synchronous memory identification

Description Submit all comments and votes

FIELD OF THE INVENTION

The invention relates generally to memory test systems, and more particularly to an automated method and system for identifying SDRAM and SGRAM memories.

BACKGROUND OF THE INVENTION

A substantial industry has evolved for the packaging of integrated circuit (IC) memory devices into subassemblies commonly referred to as memory modules. The memory module is a more practical increment of memory than a single IC, and has enjoyed some industry standardization with regard to means of connection, operating voltages, definition of connector pins, and operation of signals. A representative standards organization is the Joint Electron Device Engineering Council (JEDEC). However, beyond that which has been standardized by industry, there are many attributes of a memory module which cannot be recognized readily by the reading of the part number, or by examination of the ICs on the module. This is a result of the wide variety of end user requirements which are placed upon the manufacture of modules.

For a memory module to be tested correctly, test parameters must be precisely identified. When module testing occurs outside of an automated environment, manual entry of test parameters becomes tedious and prone to human error. In an automated environment, the incorporation of a small non-volatile memory device known as "serial presence detect bits" into a memory module for the storage of memory parameters has not solved the test parameter identification problem. The contents of these non-volatile memories themselves are generally incomplete, not standardized, and not initialized and tested at the point of manufacture.

A synchronous memory test system has been developed which provides for the automatic identification (ID) of synchronous memory modules, and for the purpose of reporting to the operator of the test system the type, configuration, size, and other characteristics of the memory module, and the establishment of all operating parameters necessary for correct testing of the module.

The memory module identification process itself is carried out in a hardware/software state machine which includes a multilayered, nested loop architecture which allows the efficient identification of all necessary memory module attributes.

Anticipating that larger and more diverse synchronous memory modules will be developed in the future, patterns representing possible control line connections are stored in tables. Table storage permits simple updating of the memory module test system without altering the operation or accuracy of the identification process.

U.S. Pat. No. 5,561,636 discloses a RAM memory which has been adapted to include a self-test feature and a plurality of memory cells arranged in rows and columns, means for selecting rows and columns, and means for simultaneously testing a plurality of cells in a plurality of rows to replace non-functioning memory cells with functioning memory cells held in reserve. The memory cells are arranged in segments with sense amplifiers coupled to each column and a second group of sense amplifiers connected to the segment to bring the test feature into effect. The present invention, by way of contrast, identifies any one of a plurality of different synchronous memories rather than a specific pre-defined memory.

U.S. Pat. No. 5,487,042 discloses a DRAM which has been modified to include circuitry that will communicate the characteristics of the DRAM including test patterns to a memory tester to accommodate a highly customized testing for the particular DRAM. By way of contrast, the present invention is not SDRAM or vendor specific, and does not depend upon the SDRAM under test to supply test patterns for use by the memory test system.

U.S. Pat. No. 5,533,194 discloses an SDRAM tester which requires hardware test circuitry to be added to the memory array "board" or memory module to control the testing of the memory array, and uses two different addressing protocols at two different rates to test all memory blocks. By contrast, the present invention uses a single addressing protocol at a single rate, and tests only a representative block in a memory array board.

U.S. Pat. No. 5,301,156 discloses a RAM which has been adapted to include a self-test circuit. The test circuit uses a signature generator to form a test signature from the RAM responses to test patterns, and a scan path to serially shift data into and out of the test circuit. The disclosed apparatus and method must be configured to operate on only a single, specific, pre-defined memory device. By way of contrast, the present invention has the capability to identify a wide variety of synchronous memories, and determines all parameters necessary to test any one of the synchronous memories being identified.

U.S. Pat. No. 5,450,364 discloses a self-refresh system which includes an oscillator coupled to a self-refresh counter, and which generates a signal to indicate that a self-refresh cycle has been completed. U.S. Pat. No. 4,451,903 discloses a method of modifying a RAM, EEPROM or EPROM to include ROM cells which are written with chip parameters including supply voltages, operating currents, programming voltages, and programming pulse-widths, as well as manufacturer's identification and mask sets. No testing occurs. By way of contrast, the present invention does not require or use identification codes stored in or with a memory unit being identified or under test in order to determine the necessary test parameters for the memory unit.

The present invention is further distinguished from U.S. Pat. Nos. 5,561,636; 5,487,042; 5,533,194; 5,301,156; 5,450,364; and 4,451,903 in that the present invention does not require hardware modifications or additions to the memory unit, memory board, or module being identified or tested.

U.S. Pat. No. 5,577,236 discloses a memory controller which is adaptive to read data from synchronous RAM modules in which the memory cells in use may vary without compromising the memory bandwidth. The memory controller has an open loop clock system which includes a system clock, and a sampling clock which provides an assortment of phase-shifted clock signals based upon the system clock. In response to a memory loading, one of the phase-shifted clock signals is selected and thereafter delayed to trigger data latches to accept data read from a memory bank after an appropriate access time. The disclosed method and apparatus requires that memory modules be precharacterized or identified and enumerated, and based upon such information, a phase-shifted sampling clock is preselected. By contrast, the present invention adapts to the memory module access time by adjusting the timing of a data sampling strobe in small increments, until during a test phase the data patterns read are identical to the data patterns written, thereby adapting to any synchronous memory access time without need for any preselections.

U.S. Pat. No. 5,570,381 discloses a method of testing SDRAM memory banks, in which data is written into a first bank at a slow tester speed, transferred between banks at a high full page burst speed, and read by the tester from the second bank at the slower tester speed. The present invention accomplishes the same result by using only the slower tester speed, and a variable word burst transfer. Further, a lower cost synchronous memory tester is made possible by employing a state machine based memory controller that obviates the need for any high-speed clock by controlling the clock enable (CKE) control line to the memory unit being identified.

U.S. Pat. No. 4,606,025 discloses a memory array test system which attempts to match the test requirements of memory arrays of different manufacturers with an array of memory testers from different manufacturers, by providing a universal tester independent language for manually entering parameter tests in accordance with designer specifications, and then using translators to make the test sequence compatible with a particular memory tester. The present invention obviates the need for processing parameters external to the memory test system by using test parameters determined by the test system itself. A lower cost synchronous memory tester is thereby made available.

U.S. Pat. No. 3,659,088 discloses a method of indicating memory chip failures in which binary numbers are assigned to each test performed on a memory cell, and an error syndrome number is provided which is a function of the numbers assigned to failed tests. A user thus must interpret the error syndrome number before deciding that the memory unit under test is sufficiently functional. By way of contrast, the present invention determines a set of test parameters which may be used to test a memory cell or unit, and conveys a message to a user which includes the test parameters without any need for an interpretive step.

SUMMARY OF THE INVENTION

A time conservative method of identifying width, depth, access time, control line configuration and part type of any of a plurality of different synchronous memories which includes a nested loop process that retrieves bit patterns from tables representative of the plurality of synchronous memories, where the nested loops are executed outer loop to inner loop in the order of bank loop, RE loop, CE loop, CS loop, DQMB loop, and part type loop, and entries in the tables are ordered such that for any given entry, bits of an entry occurring after the given entry are either a member of a superset or do not intersect bits of previous entries, and bits of an entry preceding the given entry are either a member of a subset or do not intersect bits of the given entry.

In one aspect of the invention, test patterns are written into and read from a synchronous memory, and the delay between issuance of a read command by the test system CPU to the synchronous memory, and reading the test patterns from the synchronous memory, is incremented in finite steps from a minimum value to a maximum value in successive write/read iterations until the write patterns are identical to the read patterns, thereby indicating that the delay is equal to the access time of the synchronous memory.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a functional block diagram of a portable synchronous memory module test system in accordance with the invention;

FIG. 2 is an overview diagram showing how the FIGS. 3-26 interrelate in illustrating the hardware and software systems comprising the invention;

FIG. 3 is a graphic illustration of the control lines of a SDRAM IC;

FIG. 4 is a graphic illustration of the control lines of a SDRAM memory module;

FIG. 5 is a functional block diagram of two parallel, interconnected banks of SDRAM ICs forming a SDRAM memory module having a 64 bit width;

FIG. 6a is a functional block diagram of the memory test system 10 of FIG. 1 in accordance with the invention;

FIG. 6b is a functional block diagram of UUT adapter 14 of FIG. 6a;

FIG. 7 is a functional block diagram of the memory test controller 116 of FIG. 6a which is used in the memory test system 10;

FIG. 8 is a logic diagram of the control enable logic 192 of FIG. 7 which is used in the memory test controller 116 of FIG. 6a;

FIG. 9 is a logic flow diagram of the states which are assumed by the state machine 150 of FIG. 6a;

FIG. 10 is a logic diagram of a system used by the memory test system 10 to convert a virtual address of the memory test system into a physical address of a synchronous memory under test;

FIG. 11 is a logic diagram of a system used by the memory test system 10 to cause address multiplexer 196 to generate physical addresses;

FIGS. 12a-12l constitute a logic flow diagram of the automated identification process used by the memory test system 10 in identifying synchronous memories;

FIG. 13 is a logic flow diagram of a test software program executed by the memory test system 10 to determine the width in bits of a synchronous memory under test;

FIGS. 14a-14b constitute a logic flow diagram of a test software program executed by the memory test system 10 to determine the depth of a synchronous memory under test;

FIG. 15 is a logic flow diagram of a test software program executed by the memory test system 10 to determine whether a trial combination of control lines is valid;

FIG. 16 is a logic flow diagram of a test software program executed by the memory test system 10 to write a word into a synchronous memory module under test;

FIG. 17 is a logic flow diagram of a test software program executed by the memory test system 10 to read a word from a synchronous memory under test;

FIGS. 18a-18b constitute a logic flow diagram of a test software program executed by the memory test system 10 to determine the burst capability of a synchronous memory under test;

FIG. 19 is a logic flow diagram of a nested loop architecture for an automated identification process executed by the memory test system 10 to identify a synchronous memory under test;

FIG. 20 is a graphical illustration of the timing signals generated by the memory test system 10 in a write to the upper eight bits of a word in synchronous memory;

FIG. 21 is a graphical illustration of the timing signals generated by memory test system 10 in a write to the lower 32 bits of a word in synchronous memory;

FIG. 22 is a graphical illustration of the timing signals generated by memory test system 10 during a self-refresh operation on synchronous memory;

FIG. 23 is a graphical illustration of the timing signals generated by memory test system 10 during a CBR refresh operation on synchronous memory;

FIG. 24 is a graphical illustration of the timing signals generated by memory test system 10 in a read from synchronous memory;

FIG. 25 is a graphical illustration of the timing signals generated by memory test system 10 during a "set mode" operation on synchronous memory;

FIG. 26 is a graphical illustration of the timing signals generated by memory test system 10 during a "set precharge" operation on synchronous memory;

FIG. 27 is a graphic illustration of the internal registers and control lines of a SGRAM IC;

FIG. 28 is a logic flow diagram which illustrates the changes which must be made to the logic flow diagram of FIG. 12a to accommodate the identification of SGRAMs;

FIG. 29 illustrates the addition of a precharge bit, register to the functional block diagram of FIG. 7 to accommodate the identification of SGRAMs;

FIGS. 30a-30c illustrate a logic flow diagram revision to FIG. 7 which is required to accommodate SGRAMs;

FIG. 31 is a graphic illustration of the control lines of an SGRAM IC; and

FIG. 32 is a functional block diagram of two parallel, interconnected banks of SGRAM ICs forming an SGRAM memory module having a 64 bit width.

DESCRIPTION OF PREFERRED EMBODIMENTS

Preferred embodiments of the present invention are now described with reference to the Figures, in which like reference numbers refer to like elements.

Before proceeding with a description of the invention, however, the following glossary of terms is presented to aid in an understanding of the invention.

GLOSSARY

Access time: Period of time (measured in nanoseconds) from the presentation of control signal (address, clock, row enable, column enable, etc.) to a memory device to the point in time when data output becomes valid.

Array: A two-dimensional arrangement of addressable memory cells within a memory IC.

Auto-ID: An intelligent tester method and system in accordance with the invention which determines the speed, width, depth, and control line configuration of a memory module.

Bank: A group of memory ICs accessed and tested in parallel. In the memory test system of the present invention, banks are numbered 0 to 3 and are up to 40 bits wide.

burst The capability of an SDRAM and an SGRAM to read or write two, four, or eight locations on successive clock cycles, given only the starting address.

CAS (column address strobe): A signal to a DRAM that loads the column portion of the memory address. (Compare RAS.) CAS latency The number of clock cycles that must elapse before data is valid.

CBR (CAS-before-RAS): Historical term denoting a standard memory refresh cycle.

CE (column enable): Synchronous counterpart to the asynchronous CAS signal on DRAM.

Clock: A continuously running memory signal that provides the timing reference for all SDRAM operations.

CS (chip select): Allows only one selected bank of memory to respond to signals in common with all memory chips.

DIMM (dual in-line memory module): In a DIMM, the front and back sets of module-edge contacts are electrically separate.

DQMB (DQ mask byte): A control line to SDRAM; it signals SDRAM to write selected 8-bit bytes within a word.

DRAM (dynamic random-access memory): A memory chip that stores 1's and 0's as charges in capacitors, allowing very high-density memories at a low cost per bit.

EEPROM (electrically erasable programmable read-only memory): A nonvolatile memory device that can retain information when power is removed. Used for storing serial PD bits on SDRAM modules.

IC (integrated circuit): As used herein, an individual memory chip mounted on a memory module.

JEDEC (Joint Electron Device Engineering Council): An industry group established to agree upon standards for electronic components such as memory devices.

ns (nanosecond): One billionth or 10.sup.-9 second.

PD (presence detect): Bits added to a memory module to allow a PC to recognize the type of memory, speed, and other properties.

RAS (row address strobe): A signal to a DRAM to load the row portion of the memory address. (Compare CAS.)

RE (row enable): Synchronous counterpart to the asynchronous RAS signal on DRAM.

Refresh: The process of cyclically reading and writing memory cells to prevent the decay of stored charges (representing 1's and 0's).

SDRAM (synchronous dynamic random-access memory): Unlike conventional DRAMs, commands and data transfers in and out of the memory device are synchronized with a high-speed clock signal.

Serial PD bits: The EEPROM method of storing the presence detect (PD) bits that enable a PC to recognize the type, size, and manufacturer data of the memory in place on the motherboard. Communication with the EEPROM is over a 1-bit-wide serial bus.

SGRAM (synchronous graphics random-access memory): A special SDRAM with color, data mask, and column address mask registers added to accelerate graphical operations in video adapters.

.mu.s (microsecond): One millionth or 10.sup.-6 second.

UUT: A unit under test.

UUT adapter: A plug-in interface board that has test sockets specific to a particular physical size and class of memory module.

Voltage bounce: A test method that varies the memory-chip voltage during testing between the minimum and maximum values preset by the operator. These variations can help to simulate power fluctuations found in some PCs.

width The number of bits that can be read or written in a single memory cycle.

FIG. 1 is a functional block diagram of a portable synchronous memory module tester 10 for testing the functional status of synchronous memories such as synchronous dynamic random access memories (SDRAMs) and synchronous graphics memories (SGRAMs). By way of example, the following discussions address SDRAMs only, but it is to be understood that SGRAMs may be accommodated as well. Where a difference in test system configuration is required, such difference is disclosed.

In operation, an SDRAM module 20 is placed into one of UUT (unit under test) sockets 11a and 11b, and a user interface program is executed to cause an indication to be visually displayed on display 12 that an ID process may be performed. When key 13b of keyboard 13 is pressed by the operator, power is applied to one of UUT sockets 11a or 11b, which respectively receive 144 pin and 168 pin memory modules. In the illustration, a SDRAM module 20 is shown inserted into the UUT 11b. Upon being initialized, the memory module tester performs a module identification process referred to as auto-ID, during which various stimuli are applied to and responses sensed from the SDRAM module 20. Upon completion of the auto-ID process, all parameters necessary for testing SDRAM module 20 are written to a `setup` portion of a test system memory in preparation for functional testing. The test parameters are available to the operator through use of menus appearing on display 12.

FIG. 2 is an overview diagram showing how FIGS. 1-12 interrelate in illustrating the hardware, software, and data structures of the present invention.

FIG. 3 illustrates graphically the control lines of a SDRAM IC 30, which has ports for the following: chip select (CS) 32, data mask byte (DQMB) 33, clock enable (CKE) 34, row enable (RE) 35, column enable (CE) 36, write enable (WE) 37, multiplexed address (A[0 . . . 11]) bus 38, timing reference clock (CLK) 39, and bi-directional data line (DQ) bus 40, without regard for active polarities. The multiplexed address bus 38 provides a means for delivering to SDRAM 30 a memory address consisting of a row address when RE 35 is asserted, and a column address when CE 36 is asserted. Bi-directional data lines (DQ[0 . . . 7]) of bus 40 allow 8-bit-parallel transfers in and out of the SDRAM which are synchronized with CLK 39. Individual SDRAMs respond to read or write commands when their CS 32, DQMB 33, CKE 34, and CE 36 inputs are simultaneously asserted. It is to be appreciated that plural SDRAM ICs as illustrated in FIG. 3 may comprise a single SDRAM module.

FIG. 4 illustrates the interface to SDRAM module 20. Signals on control lines CS051, CS152, CS253, and CS354 are chip selects; signals on control lines DQMB055, DQMB156, DQMB257, DQMB358, DQMB459, DQMB560, DQMB661, and DQMB762 are data byte masks; signals on control lines CKE063 and CKE164 are clock enables; signals on control lines RE065 and RE166 are row enables; and signals on control lines CE067 and CE168 are column enables. WE 37 is the write enable; A[0 . . . 11] 38 is the multiplexed address bus, and CLK 39 is the system clock signal. All of the aforementioned signals originate from the memory test controller of the memory module test system, and are synchronized to CLK 39. For purposes of illustration, bi-directional data bus DQ[0 . . . 63] 70 aggregates eight 8-bit-wide buses of the constituent SDRAMs into one 64-bit bus. It is understood, however, that a SDRAM memory module could be comprised of more or fewer than eight SDRAM ICs. All transfers on DQ[0 . . . 63] 70 are synchronized to CLK 39.

FIG. 5 illustrates how two banks of 16 eight-bit-wide SDRAM ICs are wired within a typical SDRAM memory module 20 with a width of 64 bits. SDRAMs D0 through D7, inclusively, are connected in parallel to SDRAMs D8 through D15 by way of 64 data lines DQ0-DQ63 of bus 70 to increase the depth or number of IC banks of module 20. Therefore, multiple, individually-selectable banks of SDRAM ICs may be connected in parallel to form memory module 20.

The uniqueness of each bank of SDRAM ICs is established by way of module control lines CS 32, DQMB 33, and CE 36. That is, the CS 32 terminal of each SDRAM IC may be connected to one of the CS051, CS152, CS253, CS354 control lines, or to a fixed logic level that constitutes permanent enable. The DQMB 33 terminal may be connected to one of the DQMB055, DQMB156, DQMB257, DQMB358, DQMB459, DQMB560, DQMB661, or DQMB762 control lines, or to a fixed logic level that provides a permanent enable. The CE 36 terminal may be connected to either of the CE067 or CE168 control lines. It thus may be seen that there are many wiring combinations which may be used to connect banks of SDRAM ICs into a single SDRAM module.

PD memory 75 is a 256 word by 8 bit, non-volatile, electrically erasable, programmable read-only memory (EEPROM) typically having stored therein memory module parameters in accordance with JEDEC guidelines. The memory 75 operates electrically separate from SDRAM signals, and has a SCL clock line 77 input, and a bi-directional serial SDA data line 79. Lines 77 and 79 are used in accordance with industry-standard I.sup.2 C bus specifications as described in "PC Peripherals for Microcontrollers", a data book by Signetics Company, a division of Philips Semiconductors, 1992. The lines 77 and 79 provide a means for tester 10 to communicate with PD memory 75.

FIG. 6a illustrates a portable SDRAM tester 10, which is employed to identify the module 20 that is inserted into the UUT socket 11a or 11b through use of the Auto-ID algorithm. Tester 10 is comprised of a 32-bit RISC CPU 80 in electrical communication by way of line 81 with address/data/control bus 82, and by way of line 83 with processor clock 84 which provides timing for CPU 80. The processor clock is a programmable synthesizer which generates a 40 MHz signal when a memory module is being tested, and an 8 MHz signal when in standby mode for reduced power consumption. ROM 90 provides a non-volatile storage for all memory test system operating software programs, and for certain constants which may be used to identify most SDRAMs. ROM 90 is in electrical communication with bus 82 by way of line 91. Further, ROM 90 is a flash ROM which may be written into only when an appropriate code is applied to its data lines. Upgrades to the software stored in the ROM thereby may be effected by way of communications interface 92.

RAM 93 provides temporary and intermediate storage for software programs, and for certain variables which allow the operating software to reference a single SDRAM module configuration having many parameters. A more efficient execution of the software thereby is provided. The RAM 93 is in electrical communication with bus 82 by way of line 94.

Communications interface 92 is in electrical communication with bus 82 by way of line 95, and provides an electrical connection to an external printer or PC connected to line 96. Display 12 is in electrical communication with I/O interface 101 by way of line 102. The I/O Interface 101 in turn is in electrical communication with bus 82 by way of line 103. Input keys 13 are in electrical communication with 1/0 interface 101 by way line 105. Power supply 106 receives control signals from I/O interface 101 by way of line 107, and supplies power to the UUTs 11a and 11b, and by way of line 108 to a PD voltage level translator (VLT) 109, to a clock VLT 110, to a control VLT 111, to an address VLT 112, and to a data VLT 113.

Power Supply 106 is a program-controlled power supply which turns the power to the UUT on and off, sets actual voltages supplied to the UUT for worst case testing, and provides voltage bouncing to simulate PC power fluctuations.

Programmable delay line 114 receives delay values from bus 82 via line 115, and receives a delay start signal from memory test controller 116 on line 117. The delay line 114 returns a delay-end signal to memory test controller 116, and to data latches 118 by way of line 119. The delay line 114 may be programmed for a delay equal to the shortest known access time for SDRAMs. The delay time then may be ratcheted up step-by-step until consistent responses are detected from module 20. The access time of the memory module under test is thereby determined.

Memory controller 116 is a field programmable gate array (FPGA) semiconductor device comprised of a state machine and control enable logic, as will be further described below. Upgrades to the internal hardware interconnection of memory controller 116 may be programmed and verified by way of communications interface 92. The controller is in electrical communication with bus 82 by way of line 120, and receives a memory clock signal from CPU 80 on line 121. The memory test controller 116 sends a module clock signal to clock VLT 110 on line 122, issues memory control signals by way of bus 123 to control VLT 111, and sends multiplexed addresses by way of bus 124 to address VLT 112. The memory test controller 116 further is in electrical communication with data latches 118 by way of line 125. The data latches 118 in turn are in bi-directional communication with bus 82 via line 126, and in bi-directional communication with data VLT 113 via line 128.

The data latches 118 allow the CPU 80 to perform a two cycle (8 bit followed by a 32 bit) write, into the data latches. Thereafter a single cycle, 40-bit write from data latches 118 to the memory module 20 occurs. Additionally, data latches 118 allow CPU 80 to perform a two-cycle (32 bit followed by an 8 bit) read of the content of the data latches following a single cycle 40-bit read from memory module 20 into the data latches.

Further functions performed by the memory controller include providing test set up signals for a memory module, refreshing a memory module to maintain memory content, commanding the memory module to perform dummy reads and writes, and writing information into and reading information from a memory module. UUT adapter 14 (which is comprised of UUT socket 11a and UUT socket 11b) is in electrical communication with clock VLT 110 via line 130, with control VLT 111 via bus 134, with address VLT 112 via bus 136, with data VLT 113 via bus 138, and with PD VLT 109 by way of lines 73a, 73b, 77 and 79.

The clock, control, and address VLTs convert the 5 volt logic level of the memory module tester to the 3.3 volt logic level of a memory module. The data VLT 113 provides bi-directional conversions between the memory module and the memory tester. The VLTs further provide for programmed electrical disconnection from a memory module.

The period of the Refresh Timer 140 can be controlled by CPU 80 by way of line 81, bus 82, and line 142, to provide an end-of-period interrupt to CPU 80 over line 144. Control thereby is transferred to an interrupt service routine stored in ROM 90 at rates appropriate for nominal and worst-case memory refresh operation of SDRAM module 20.

A crystal-controlled oscillator 141 provides an accurate reference signal having a frequency of 3.6864 MHz over line 143 to the refresh timer 140, and over line 145 to the communications interface 92. The refresh timer controls interrupts to the CPU 80. The communication interface provides information to other systems for further processing and/or display by way of line 96.

In operation, CPU 80 provides a derived system clock on line 121 for the memory test controller 116, while executing software program codes stored in ROM 90 and using RAM 93 for temporary, intermediate, and variables storage. Programmable delay line 114 has a delay set in increments of approximately 40/256ths of a nanosecond under software control. Display 12 and input keys 13 provide the user interface, and a means of prompting the operator and displaying the results of the auto-ID functionality which will be explained in more detail below. Memory test controller 116 generates all timing for the UUT 11. Controlled power supply 106 allows the power to the UUT 11 and VLTs 110, 111, 112, and 113 to be switched on and off under control of the software stored in ROM 90.

CPU 80 is comprised of a 32-bit RISC processor operating at 20 MHz, and associated peripherals including a reset circuit, an address latch, and an address decoder. The 32-bit RISC processor is identified by part number 79R3041-20J, and is available from Integrated Device Technology, Inc., 2975 Stender Way, Santa Clara, Calif. 95054.

Display 12, is comprised of (1) a graphical 128.times.64-pixel liquid-crystal display (LCD) assembly identified by part number HG12602NG, which is available from Hyundai, Central Commerce Building, 8F-1, No. 181, Fu-Hsing N. Road, Taiwan, R.O.C.; (2) a red-color "fail" LED; and (3) green-color "pass" LED.

Input keys 13 provide a change in logic levels when pressed. The logic levels in turn are conveyed to I/O interface 101 and read by the CPU 80.

The tester system electronics and power supply 106 are energized by a 12-volt DC power supply. Controlled power supply 106 provides a +3.3 volt source which is required by SDRAM module 20, and includes an I/O port for control signals. Power supply 106 is comprised of key components identified by part number DS 1267-10 (dual digital potentiometer chip available from Dallas Semiconductor Corp., 4401 South Beltwood Parkway, Dallas, Tex. 75244-3292), and part number TL594C, and includes a pulse-width modulation control IC available from Texas Instruments, P.O. Box 655303, Dallas, Tex. 75265-5303; for which many application notes are available in the industry.

Programmable delay line 114 is identified by part number AD9501JP, and is available from Analog Devices, One Technology Way, P.O. Box 9106, Norwood, Mass. 02062-9106.

Memory test controller 116 is identified by part number is pLSI 1048E-70LQ, and is a high-density programmable logic device which is available from Lattice Semiconductor Corp., 5555 Northeast Moore Court, Hillsboro, Oreg. 97124.

Voltage level translators 110, 111, 112, and 113, are identified by part number 74LVX2425WM, and are supplied as an 8-bit, dual supply, translating transceiver IC available from National Semiconductor Corp., 2900 Semiconductor Drive, Santa Clara, Calif. 95052-8090.

Communications interface 92 and refresh timer 140 are identified by part number SCN2681, as a dual asynchronous receiver/transmitter IC available from Philips Semiconductors, Signetics Company, 811 East Arques Avenue, Sunnyvale, Calif. 94088-3409. Line 96 is identified as an electrical interface having part number MAX238 RS-232, and is available as a level translator IC that may be purchased from Maxim Integrated Products, Inc., 120 San Gabriel Drive, Sunnyvale, Calif. 94086.

Data latches 118 are comprised of three units, each of which is identified by part number IDT74FCT16543AT as a 16-bit, non-inverting, latched transceiver available from Integrated Device Technology, Inc., 2975 Stender Way, Santa Clara, Calif. 95054-3090.

Referring to FIG. 6b UUT adapter 14 is detachable from tester 10 and comprises a 144 pin SO DIMM UUT socket 11a and a 168 pin DIMM UUT socket 11b. The module clock signal 130 is independently buffered by clock buffers 71a and 71b to provide second module clock signals CLK 39a and 39b, respectively, to UUT sockets 11a and 11b. The clock buffers 71a and 71b may be identified by part number PI49FCT3805S, and is available from Pericom Semiconductor Corp., 2380 Bering Drive, San Jose, Calif. 95131. Module sense lines 73a and 73b are respectively grounded when a memory module 20 is inserted into either of the UUT sockets 11a or 11b, thereby providing hardware means for auto-ID software to sense package type, the (SO DIMM 144 or DIMM 168) and enable clock buffers 71a and 71b to drive the clock signals 39a and 39b. Thus, for minimum electromagnetic radiation, the clock signal lines 39a and 39b, are not driven when there is no memory module in either UUT socket 11a or UUT socket 11b.

Module control signals bus 134 comprises chip select lines CS0, CS1, CS2, and CS3; data byte mask lines DQMB0, DQMB1, DQMB2, DQMB3, DQMB4, DQMB5, DQMB6, and DQMB7; clock enable lines CKE0 and CKE1; row enable lines RE0 and RE1; column enable lines CE0 and CE1; define special function line DSF; and write enable line WE. Bus 134 is in electrical communication with both UUT sockets 11a and 11b.

Module address bus 136 comprises fourteen multiplexed lines A.sub.0 -A.sub.13, and is in electrical communication with both UUT sockets 11a and 11b. Module Serial clock (SCL) line 77 and bi-directional serial data (SDA) line 79 provide connections for an I.sup.2 C (inter-IC) electrical interface to both UUT sockets 11a and 11b. UUT power line 108 energizes both clock buffers 71a and 71b, and both UUT sockets 11a and 11b.

Table A shows the signal connection of each line of the 40-bit data bus 138 leading from data VLT 113 to both UUT sockets 11a and 11b. The high 8 bits of data bus 138 (D.sub.32 through D.sub.39) connect to synchronous DRAM modules having "check bits", as may be denoted by terminals CB0 through CB15 on UUT sockets 11a and 11b. Check bits are most commonly used on error-correcting type memory modules with widths of 72 and 80 bits.

TABLE A DATA VLT 113 UUT SOCKET 11a UUT SOCKET 11b BUS 138 BUS 138a BUS 138b BUS 134a BUS 138b D.sub.0 DQ0 DQ32 DQ0 DQ32 D.sub.1 DQ1 DQ33 DQ1 DQ33 . . . . . . . . . . . . . . . D.sub.31 DQ31 DQ63 DQ31 DQ63 D.sub.32 CB0 CB8 CB0 CB8 D.sub.33 CB1 CB9 CB1 CB9 . . . . . . . . . . . . . . . D.sub.39 CB7 CB15 CB7 CB15

Software recognition of a UUT adapter's identification is provided by CPU 80 upon reading the state of eight adapter ID lines 85 by way of I/O interface 101. On UUT adapter 14, adapter ID lines 85 are normally in the high or logic "1" state, and are selectively grounded with straps 86 wherever it is desired to read a logic "0" in some bit position. Thus, one adapter may be strapped for a code of 01010001 or hexadecimal 51, and comprise UUT sockets for memory modules with 144 pin SO DIMM and 168 pin DIMM packages. Another adapter may be strapped for a code of 01010011 or hexadecimal 53, and comprise one or more sockets for synchronous graphics RAM, and so forth. Further, reading a code of 11111111 or hexadecimal FF signifies that no UUT adapter is installed.

FIG. 7 is a functional block diagram of memory test controller 116 which provides all timing, control and addressing for the memory module under test. The system clock signal on line 121 provides state machine 150 the timing control to sample all incoming signals and to clock state transitions. The system clock signal on line 121 further is delayed by delay element 157 and output as a reference clock signal on line 122. The heart of the memory test controll