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Claims  |
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What is claimed is:
1. A semiconductor component assembly, comprising:
a semiconductor component comprising an active surface and a back side
surface, said back side surface having a substantially non-planar texture
wherein said substantially non-planar texture of the back side surface has
a peak to valley amplitude measuring between about 5 .mu.m and 25 .mu.m.
2. The semiconductor component assembly of claim 1, wherein said
semiconductor component is a semiconductor wafer.
3. The semiconductor component assembly of claim 1, wherein said
semiconductor component is either a singulated semiconductor die or a
partial wafer comprising a plurality of semiconductor die locations.
4. The semiconductor component assembly of claim 1, wherein the
substantially non-planar texture of the back side surface has a sinuate
cross-sectional contour.
5. The semiconductor component assembly of claim 1, wherein the
substantially non-planar texture of the back side surface has a saw-tooth
cross-sectional contour.
6. The semiconductor component assembly of claim 1, wherein the
substantially non-planar texture of the back side surface has a square
cross-sectional contour.
7. The semiconductor component assembly of claim 1, wherein the
substantially non-planar texture of the back side surface has a contour of
geometric cross-sectional configuration.
8. The semiconductor component assembly of claim 1, wherein the
substantially non-planar texture of the back side surface has
cross-sectional contour of irregular configuration.
9. The semiconductor component assembly of claim 1, wherein the
substantially non-planar texture of the back side surface has a peak to
peak amplitude measuring between about 5 .mu.m and 25 .mu.m.
10. The semiconductor component assembly of claim 1, wherein the
substantially non-planar texture of the back side surface has a valley to
valley amplitude measuring between about 5 .mu.m and 25 .mu.m.
11. The semiconductor component assembly of claim 1, wherein the
substantially non-planar texture of the back side surface is formed of a
plurality of substantially concentric circles.
12. The semiconductor component assembly of claim 1, wherein the
substantially non-planar texture of the back side surface is formed in a
pattern of wedges about a central point.
13. The semiconductor component assembly of claim 1, wherein the
substantially non-planar texture of the back side surface is formed in a
pattern comprising a plurality of rectangles.
14. The semiconductor component assembly of claim 13, wherein the
substantially non-planar texture of the back side surface is formed in a
pattern comprising a plurality of squares.
15. The semiconductor component assembly of claim 1, wherein the
substantially non-planar texture of the back side surface is formed in a
spiral pattern.
16. The semiconductor component assembly of claim 1, wherein the
substantially non-planar texture of the back side surface is formed in a
geometric pattern.
17. The semiconductor component assembly of claim 1, further comprising an
encapsulant adhered to the back side surface in substantial conformity
with the substantially non-planar texture of the back side surface.
18. The semiconductor component assembly of claim 1, further comprising:
a carrier substrate; and
a die attach adhesive positioned between the back side surface of said
semiconductor component and said carrier substrate, said die attach
adhesive being adhered to the substantially non-planar texture of the back
side surface of said semiconductor component in substantial conformity
therewith.
19. The semiconductor assembly of claim 18, wherein said carrier substrate
is ceramic.
20. The semiconductor assembly of claim 18, wherein said carrier substrate
is metallic.
21. The semiconductor assembly of claim 18, wherein said semiconductor
substrate is organic.
22. A semiconductor component assembly, comprising:
at least a portion of a semiconductor wafer including an active surface and
a back side surface, said back side surface having a substantially
non-planar texture; and
wafer tape attached intermittently to portions of the back side of said at
least a portion of said semiconductor wafer.
23. A semiconductor component assembly comprising:
a plurality of singulated semiconductor dice each including an active
surface and a back side surface, said back side surface having a
substantially non-planar texture; and
wafer tape attached intermittently to portions of the back side surface of
said plurality of singulated semiconductor dice.
24. A method of fabricating a semiconductor component comprising:
providing a semiconductor component having an active surface and a back
side surface; and
texturing the back side surface of said semiconductor component to create a
substantially non-planar surface over the back side surface wherein said
substantially non-planar surface has a peak to valley amplitude measuring
between about 5 .mu.m and 25 .mu.m.
25. The method of claim 24, further comprising providing the semiconductor
component as a semiconductor wafer.
26. The method of claim 24, further comprising providing the semiconductor
component as a portion of a semiconductor wafer.
27. The method of claim 24, further comprising providing the semiconductor
component with a plurality of semiconductor die locations thereon.
28. The method of claim 24, wherein texturing the back side surface further
comprises grinding or scribing the back side surface.
29. The method of claim 24, wherein texturing the back side surface further
comprises selectively masking and etching the back side surface.
30. The method of claim 24, wherein texturing the back side surface
includes creating said substantially non-planar surface having a peak to
peak amplitude between about 5 .mu.m and 25 .mu.m.
31. The method of claim 24, wherein texturing the back side surface
includes creating said substantially non-planar surface having a valley to
valley amplitude between 5 .mu.m and 25 .mu.m.
32. The method of claim 24, further comprising singulating the
semiconductor component to define a plurality of individual semiconductor
dice, each having a portion of the substantially non-planar surface on a
back side thereof.
33. The method of claim 32, further comprising attaching at least some of
the individual semiconductor dice by the back side thereof to a supporting
structure with a die attach material in substantially continuous contact
with said portion of said substantially non-planar surface.
34. The method of claim 32, further comprising at least partially
encapsulating at least some of the individual semiconductor dice with an
encapsulant compound disposed in substantially continuous contact with
said portion of said substantially non-planar surface.
35. The method of claim 24, wherein texturing the back side surface
comprises forming a predetermined pattern in the back side surface.
36. The method of claim 35, further comprising defining the predetermined
pattern in a form of peaks and intervening valleys.
37. The method of claim 24, further comprising intermittently adhering the
back side surface of the semiconductor component to semiconductor wafer
tape. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for patterning,
shaping and/or altering the backside surface of a semiconductor die. The
present invention improves adhesion between a back side surface of a
semiconductor die and either a die attach adhesive or encapsulation
compound, reduces adhesive contamination from semiconductor wafer tape
used in wafer processing, and reduces shear stress along the interface
between the semiconductor die back side surface and either the die attach
adhesive and/or encapsulation compound.
2. State of the Art
In a typical integrated circuit manufacturing process, a plurality of sets
of integrated circuit patterns are simultaneously formed in discrete
locations on a surface of a semiconductor wafer by a series of layer
deposition and etching processes, as known in the art. Each set of the
integrated circuit patterns is generally formed in a series of rectangular
formats on a surface of the semiconductor wafer. Each set of integrated
circuit patterns is separated from another set of integrated circuit
patterns on the surface of the wafer by an area located therebetween where
no integrated circuits or circuits are located on the surface of the
wafer. Such an area separating each set of integrated circuits on the
surface of the wafer being generally referred to as a "street area" on the
surface of the wafer. After the sets of integrated circuit patterns are
fully formed, the semiconductor wafer is diced by a wafer sawing machine,
as known in the art, along the street areas of the semiconductor wafer
separating the semiconductor wafer into a plurality of individual
semiconductor dice having a plurality of integrated circuits. These
individual semiconductor dice can then either be packaged within
protective packages or incorporated into appropriate electronic circuits
as unpackaged, or "bare", semiconductor die.
The term "semiconductor wafer" is used herein to denote any solid
semiconductor surface, such as is provided by a silicon, gallium arsenide
or indium phosphide wafer sliced transversely from a crystal ingot, or a
layer of such semiconductor material formed on glass, ceramic, sapphire,
or other supporting carrier, as known in the art.
Once a semiconductor wafer has been sliced or otherwise formed, such as
being sawed from a crystal ingot, a surface of the semiconductor wafer may
undergo a rough polish followed by chemical-mechanical polishing process
("CMP process") to free the surface of irregularities and/or saw damage
for the subsequent formation of the integrated circuit patterns thereon.
Rough polishing of a surface of the semiconductor wafer generally includes
an abrasive, slurry lapping process, as known in the art. The CMP process
used after a rough polish of a surface of the wafer includes a combination
of chemical etching and mechanical buffing wherein a mild etchant solution
is flooded over the semiconductor wafer forming a thin etched chemical
layer of a surface of the semiconductor wafer that is removed by the
mechanical buffing action. The combination of the rough polish followed by
CMP process results in a mirror-like finish on a surface of the
semiconductor wafer. The term "mirror-like finish" is generally defined as
a semiconductor wafer surface flatness value typically ranging from 3 to 4
.mu.m as measured by the maximum peak-to-valley deviation of a
semiconductor wafer surface from a reference plane extending thereover.
Generally, semiconductor wafers are initially sliced or otherwise
fabricated having a thickness greater than is desired for a finished
integrated circuit semiconductor die formed therefrom. A thick
semiconductor wafer is more robust, which minimizes warpage and breakage
that can result from various heating processes, as well as other
processes, during the formation of the integrated circuit patterns for the
semiconductor dice on a polished surface of the semiconductor wafer.
However, the thick semiconductor wafer is typically thicker than is desired
for packaging of the individual semiconductor die, or too thick for use
with processing equipment and fixtures in subsequent semiconductor die
processing and/or encapsulation steps. Therefore, it is usually necessary,
after the integrated circuit patterns are defined on the polished surface
of the semiconductor wafer, to grind or otherwise remove a portion of the
back side surface of the semiconductor wafer (i.e., the side opposite to
the polished surface having a mirror-like finish of the semiconductor
wafer) in order to reduce the semiconductor wafer thickness prior to the
semiconductor wafer being diced into individual semiconductor die.
Suitable grinding, sawing machines, and other processes and equipment for
removing excess wafer depth on the semiconductor wafer back side surface
are well known in the art.
To prevent movement of portions of the semiconductor wafer during the
sawing process used to form individual semiconductor dice, a piece of
semiconductor wafer tape is temporarily secured to the back side surface
of the semiconductor wafer. Semiconductor wafer tape typically comprises
an adhesive, a base film, and a release liner. The semiconductor wafer
tape typically has a thickness in the range of about 5 to 15 .mu.m. The
semiconductor wafer tape adhesive is typically composed of five
components: a base polymer, a cross-linking agent, an oligomer, a
photo-initiator, and an additive agent. The base polymer comprises the
main structural element of the adhesive of the semiconductor wafer tape.
The oligomer serves to adjust the adhesive strength and hardness of the
adhesive, so that an individual integrated circuit semiconductor die can
be easily removed from the semiconductor wafer tape. The cross-linking
agent is designed to enhance the cohesion of the adhesive of the
semiconductor wafer tape. The photo-initiator enhances the degree of
bonding by creating radicals during exposure to UV radiation after the
semiconductor wafer tape is applied to the back side surface of the
semiconductor wafer. Lastly, the additive agent acts to modify the
strength of the adhesive of the semiconductor wafer tape independently of
the oligomer. After application to the back side of the semiconductor
wafer, the semiconductor wafer tape is exposed to ultraviolet radiation to
trigger a chemical reaction to render the tape adhesive. (See, M. Amagai,
et al., "Cracking Failures in Lead-On-Chip Packages Induced by Chip Back
side Contamination", IEEE Transactions On Components, Packaging And
Manufacturing Technology, Part B, Vol. 18, No. 1, pp. 119-126 (1995)
(hereinafter "the Amagai article")).
After sawing the semiconductor wafer to form individual semiconductor die,
the individual, or "singulated", semiconductor dice are removed from the
semiconductor wafer tape. Although the taping of the semiconductor wafer
is necessary, it results in adhesive and/or residues (primarily base
polymer, oligomer, and additives) remaining on the back side of each of
the individual semiconductor dice. These contaminants (adhesive and/or
residues) affect the quality of the bond between the individual
semiconductor die and an encapsulation compound (such as an epoxy molding
resin) which may surround the semiconductor die used in the packaging of
the die, or the quality of the bond between the semiconductor die and a
substrate to which the semiconductor die may be mounted by a die attach
adhesive (such as an epoxy adhesive). The failure to form a high quality
bond may then result in interfacial delamination between the back side
surface of the semiconductor die and either the encapsulation compound or
the die attach adhesive. Thereafter, moisture absorbed into either the
encapsulation compound or the die attach adhesive may collect in the
delaminated areas where subsequent higher temperatures can convert the
moisture to steam. The formation of steam may crack either the
encapsulation compound or die attach adhesive or further delaminate the
semiconductor die from either the encapsulation compound or die attach
adhesive.
Furthermore, interfacial delamination caused by the lack of a high quality
bond may be exacerbated by thermal mismatch due to differing coefficients
of thermal expansion ("CTE") between the semiconductor die and either the
encapsulation compound or the die attach adhesive. As the semiconductor
die is thermally cycled by heating and cooling during fabrication
processes, the interfacial delamination causes a high stress concentration
in any encapsulation compound (particularly at a corners thereof) or the
die attach adhesive which, in turn, can cause cracks. Once cracks are
formed in either the encapsulation compound or die attach adhesive, the
semiconductor package is susceptible to contamination which can render the
semiconductor die inoperative.
Moreover, as higher performance, lower cost, increased miniaturization of
components and greater packaging density of semiconductor die occur,
related semiconductor die problems increase, such as package cracking,
contamination, poor semiconductor die-to-encapsulation compound adhesion,
and poor semiconductor die-to-substrate adhesion.
In an effort to combat these problems, various techniques have been
suggested. Two common temporary solutions include baking the moisture out
of the mold compound to ensure a low moisture content within the package,
and placing the packaged semiconductor device in a "dry package" for
shipping purposes. However, neither solution prevents moisture from
entering the packaged semiconductor device at a later time, such as at the
customer's site after the device is removed from the shipping container
materials. Furthermore, these solutions do not address the CTE problems.
Moreover, if the semiconductor die has delaminated even slightly in the
from the encapsulation compound forming the package, the package may be
subject to moisture penetration after installation causing the package to
crack or delaminate when exposed to sufficient heat.
U.S. Pat. No. 5,583,372 (hereinafter "the '372 Patent"), issued to King et
al., assigned to the assignee of the present invention, discloses a
semiconductor die including a metal layer deposited thereon for enhancing
adhesion between the semiconductor die and a mold compound (i.e., an
encapsulant compound). The metal layer is substantially oxide free and
provides a uniform wetting surface for better adhesion. However, the
semiconductor die of the '372 Patent does not prevent or reduce
contamination due to the semiconductor wafer tape. Furthermore, the '372
Patent requires additional materials and fabrication processing;
specifically, depositing approximately 50 micro inches of copper on the
back side surface of the semiconductor die and approximately 2 to 3 micro
inches of palladium over the copper layer to form the metal layer.
U.S. Pat. No. 5,313,102 (hereinafter "the '102 Patent"), issued to Lim et
al., discloses a "leads-on-chip" (hereinafter "LOC") semiconductor package
device wherein a polyimide coating is placed on a back side surface of the
integrated circuit prior to encapsulation to improve adhesion between the
back side surface of the integrated circuit and the encapsulation
compound. However, the semiconductor package device of the '102 Patent
does not prevent or reduce contamination to the back side surface of the
semiconductor wafer or to the polyimide coating due to the semiconductor
wafer tape. Moreover, the polyimide coating fails to correct shearing
problems due to differing CTEs between the semiconductor wafer and die
attach adhesives or encapsulants.
U.S. Pat. No. 5,756,380 (hereinafter "the '380 Patent"), issued to Berg et
al., discloses a method for making moisture resistant semiconductor
devices, such as a plastic ball grid array packages, having a
semiconductor die attached to an organic substrate by a silicone based die
attach material after undergoing a cleaning operation to remove
contaminants from the back side surface of the semiconductor die and prior
to encapsulation. However, the '380 Patent requires the added processing
step of cleaning using an ultraviolet light and ozone cleaning operation
and does not compensate for, reduce, and/or eliminate potential shearing
problems or thermal mismatching problems due to materials having
dissimilar CTEs.
Finally, the Amagai article, previously referenced, discloses that
adhesives with a high elastic modulus (i.e. materials which could be
peeled without leaving residues) eliminate semiconductor wafer tape
contamination and also improve the wettability of the chip back side
surface. However, usage of the new semiconductor wafer tape disclosed in
the Amagai article does not compensate for nor reduce or eliminate the
potential thermal mismatching problems and resultant shear forces due to
materials having dissimilar CTEs.
Thus, it can be appreciated that it would be advantageous to develop a
semiconductor die and a technique to fabricate the same which overcomes
the problems associated with contamination by the semiconductor wafer
tape, thermal mismatch, and poor back side adhesion between the back side
surface of the semiconductor die and either the encapsulation compounds or
die attach adhesives.
SUMMARY OF THE INVENTION
The present invention relates to a method and an apparatus for reducing or
substantially eliminating delamination and cracking damage to a packaged
semiconductor device assembly due to thermal mismatch and/or semiconductor
wafer tape contamination, as well as subsequent cracking and moisture
penetration resulting from contamination by the semiconductor wafer tape.
The present invention provides a semiconductor die having a physically
altered back side surface that improves adhesion between the back side
surface of the die and either the die attach adhesives or encapsulation
compounds and reduces or substantially eliminates shear forces acting upon
the back side surface of the die due to thermal expansion materials
mismatch.
An embodiment of the present invention comprises a packaged semiconductor
device assembly including a semiconductor die including, in turn, an
active surface and a back side surface. The back side surface of the
semiconductor die exhibits a substantially non-planar texture that may be
contoured in various different shapes at a variety of different depths as
measured from peak-to-valley of each contour. In other words, the back
side surface of the semiconductor die may exhibit, in cross-section,
contours, including sinuate, square, triangular (saw tooth), and the like.
The depth of the contours, from peak to valley, is generally greater than
the thickness of the adhesive on the semiconductor wafer tape to be used
on the semiconductor wafer from which the die is formed. The contours of
the back side surface of the semiconductor die are preferably no greater
than 25 microns in depth, although this dimension is not a limitation
critical to the invention.
The substantially non-planar textured back side surface may be created
during fabrication of the semiconductor wafer (e.g., such as during the
removal of the portion of the back side of the semiconductor wafer, as
previously discussed) wherein conventional processes, such as grinding and
masking and etching processes, may be used to texture and shape the
semiconductor wafer's back side surface. Of course, other conventional
fabrication processes, such as scribing, lapping, metallizing, and the
like may be used. Furthermore, the substantially non-planar textured back
side surface may be formed in a variety of patterns (the features of which
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