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| United States Patent | 6185644 |
| Link to this page | http://www.wikipatents.com/6185644.html |
| Inventor(s) | Farmwald; Michael (Berkeley, CA), Horowitz; Mark (Palo Alto, CA) |
| Abstract | A memory system having a master device and a plurality of memory
subsystems, including first and second memory subsystems coupled to a
first bus. Each memory subsystem includes a plurality of memory devices.
The master device transmits a request for a read operation onto the first
bus to access data from at least one memory device included in at least
one memory subsystem. The first and second memory subsystems each include
a transceiver device, a bus, and first and second memory devices. Each
transceiver device connects to the first bus. The bus of each memory
subsystem connects to each respective transceiver device, wherein each
transceiver device is coupled between the first bus and each respective
memory subsystem bus. The first and second memory devices in each memory
subsystem are coupled respective transceiver devices via respective buses. |
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Title Information  |
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Drawing from US Patent 6185644 |
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Memory system including a plurality of memory devices and a transceiver
device |
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| Publication Date |
February 6, 2001 |
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| Filing Date |
January 19, 2000 |
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| Parent Case |
This application is a continuation of application Ser. No. 09/239,522,
filed Jan. 29, 1999 now U.S. Pat. No. 6,044,426; which is a continuation
of application Ser. No. 09/098,387, filed on Jun. 16, 1998 (now U.S. Pat.
No. 5,928,343); which is a divisional of application Ser. No. 08/762,139,
filed Dec. 9, 1996 (now U.S. Pat. No. 5,809,263); which is a continuation
of application Ser. No. 08/607,780, filed on Feb. 27, 1996 (now
abandoned); which is a continuation of application Ser. No. 08/222,646,
filed on Mar. 31, 1994 (now U.S. Pat. No. 5,513,327); which is a
continuation of application Ser. No. 07/954,945, filed on Sep. 30, 1992
(now U.S. Pat. No. 5,319,755); which is a continuation of application Ser.
No. 07/510,898, filed on Apr. 18, 1990 (now abandoned). |
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Title Information  |
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References  |
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| *references marked with an asterisk below are user-added references |
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U.S. References |
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Foreign References |
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Foreign References |
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Other References |
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| | Reference | Relevancy | Comments | J Peterson, "System Level Concerns Set Performance Gains", High Performance Systems, pp. 71-77 (Sep. 89).
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. May,2007 |      Your vote accepted [0 after 0 votes] | | M. Kimoto, "A 1.4ns/64kb RAM with 85ps/3680 Logic Gate Array", 1989 IEEE Custom Integrated Circuits Conference.
. May,2007 |      Your vote accepted [0 after 0 votes] | | D. Wendell et. al., "A 3.5ns, 2Kx9 Self Timed SRAM", 1990 IEEE Symposium on VLSI Circuits (Feb. 1990).
. May,2007 |      Your vote accepted [0 after 0 votes] | | E.H. Frank "The SBUS: Sun's High Performance System Bus for RISC Workstations" Sun Microsystems Inc. 1990.. May,2007 |      Your vote accepted [0 after 0 votes] | | |
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