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Memory system including a plurality of memory devices and a transceiver device    
United States Patent6185644   
Link to this pagehttp://www.wikipatents.com/6185644.html
Inventor(s)Farmwald; Michael (Berkeley, CA), Horowitz; Mark (Palo Alto, CA)
AbstractA memory system having a master device and a plurality of memory subsystems, including first and second memory subsystems coupled to a first bus. Each memory subsystem includes a plurality of memory devices. The master device transmits a request for a read operation onto the first bus to access data from at least one memory device included in at least one memory subsystem. The first and second memory subsystems each include a transceiver device, a bus, and first and second memory devices. Each transceiver device connects to the first bus. The bus of each memory subsystem connects to each respective transceiver device, wherein each transceiver device is coupled between the first bus and each respective memory subsystem bus. The first and second memory devices in each memory subsystem are coupled respective transceiver devices via respective buses.
   














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Drawing from US Patent 6185644
Memory system including a plurality of memory devices and a transceiver
     device - US Patent 6185644 Drawing
Memory system including a plurality of memory devices and a transceiver device
Inventor     Farmwald; Michael (Berkeley, CA) , Horowitz; Mark (Palo Alto, CA)
Owner/Assignee     Rambus Inc. (Mountain View, CA)
Patent assignment
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Publication Date     February 6, 2001
Application Number     09/487,524
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     January 19, 2000
US Classification     710/301 365/189.05
Int'l Classification    
Examiner     Auve; Glenn A.
Assistant Examiner    
Attorney/Law Firm     Steinberg; Neil A.
Address
Parent Case     This application is a continuation of application Ser. No. 09/239,522, filed Jan. 29, 1999 now U.S. Pat. No. 6,044,426; which is a continuation of application Ser. No. 09/098,387, filed on Jun. 16, 1998 (now U.S. Pat. No. 5,928,343); which is a divisional of application Ser. No. 08/762,139, filed Dec. 9, 1996 (now U.S. Pat. No. 5,809,263); which is a continuation of application Ser. No. 08/607,780, filed on Feb. 27, 1996 (now abandoned); which is a continuation of application Ser. No. 08/222,646, filed on Mar. 31, 1994 (now U.S. Pat. No. 5,513,327); which is a continuation of application Ser. No. 07/954,945, filed on Sep. 30, 1992 (now U.S. Pat. No. 5,319,755); which is a continuation of application Ser. No. 07/510,898, filed on Apr. 18, 1990 (now abandoned).
Priority Data    
USPTO Field of Search     710/101 710/104 710/102 365/189.01 365/189.05 365/230.03 365/230.04 365/230.08
Patent Tags     memory including plurality memory devices transceiver
   
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