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Temporary package, system, and method for testing semiconductor dice and chip scale packages    

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United States Patent6188232   
Link to this pagehttp://www.wikipatents.com/6188232.html
Inventor(s)Akram; Salman (Boise, ID); Wood; Alan G. (Boise, ID); Farnworth; Warren M. (Nampa, ID)
AbstractAn improved interconnect for semiconductor dice, a method for testing dice using the interconnect, and a method for fabricating the interconnect are provided. The interconnect includes dense arrays of contact members configured to establish temporary electrical communication with contact locations on a die under test. In addition, the interconnect includes patterns of multi level conductors formed on different levels of the substrate and separated by insulating layers. The multi level conductors can be formed with a higher density and with less cross talk than planar conductors to permit high speed testing of dice having a large number of bond pads. The interconnect can be configured for use with a temporary package for housing a single die for burn-in or other testing. Electrical paths between terminal contacts on the package and the multi level conductors on the interconnect can be formed by microbump tape having low resistance microbumps bonded to the multi level conductors.
   














 Title Information Submit all comments and votes
 
Patent Text Patent PDF Print Page Summary File History
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Inventor     Akram; Salman (Boise, ID); Wood; Alan G. (Boise, ID); Farnworth; Warren M. (Nampa, ID)
Owner/Assignee     Micron Technology, Inc. (Boise, ID)
Patent assignment
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Company News
Publication Date     February 13, 2001
Application Number     09/106,688
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     June 29, 1998
US Classification     324/755 324/765
Int'l Classification     G01R 031/02 G01R 031/26
Examiner     Metjahic; Safet
Assistant Examiner     Hollington; Jermele M.
Attorney/Law Firm     Gratton; Stephen A.
Address
Parent Case     CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 08/777,822 filed on Dec. 31, 1996, now U.S. Pat. No. 5,834,945.
Priority Data    
USPTO Field of Search     324/755 324/754 324/765 324/158.1
Patent Tags     temporary package, system, testing semiconductor dice and chip scale packages
   
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 U.S. References
 
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6094058
Hembree

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Wood

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Wood

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 Technical Review Submit all comments and votes
 Claims Submit all comments and votes
 


What is claimed is:

1. A temporary package for testing a semiconductor die or a semiconductor package comprising:

a base adapted to retain the die or the package, the base comprising a plurality of terminal contacts; and

an interconnect on the base comprising a substrate, a plurality of first contacts on the substrate configured to electrically contact a plurality of second contacts on the die or the package, and a plurality of multi level conductors on the substrate in electrical communication with the first contacts and embedded in a plurality of insulating layers on the substrate; and

a tape on the base electrically connecting the first contacts to the terminal contacts.

2. The temporary package of claim 1 wherein the tape comprises at least one microbump bonded to the interconnect.

3. The temporary package of claim 1 wherein the interconnect comprises an array of pads in electrical communication with the conductors and bonded to the tape.

4. A temporary package for testing a semiconductor die or a semiconductor package comprising:

a base adapted to retain the die or the package, the base comprising a plurality of terminal contacts and conductive traces in electrical communication with the terminal contacts;

an interconnect on the base comprising a substrate, a plurality of first contacts on the substrate for electrically contacting a plurality of second contacts on the die or the package, a plurality of conductors on the substrate located on different planes, and a plurality of insulating layer on the substrate electrically isolating the conductors; and

a tape comprising metal bumps bonded to the conductors on the interconnect and to the conductive traces on the base to establish electrical communication therebetween.

5. The temporary package of claim 4 wherein the second contacts comprise second metal bumps and the first contacts comprise indentations configured to retain the second metal bumps.

6. The temporary package of claim 4 wherein the second contacts comprise second metal bumps and the first contacts comprise indentations (with) and projections in the indentations configured to penetrate the second metal bumps.

7. A temporary package for testing a semiconductor die or a semiconductor package having a plurality of bumps comprising:

a base configured to retain the die or the package, the base comprising a plurality of terminal contacts connectable to test circuitry, and a plurality of conductive traces in electrical communication with the terminal contacts;

an interconnect on the base comprising a substrate, a plurality of first contacts comprising indentations on the substrate and conductive layers on the indentations configured to retain and electrically contact the bumps, and a plurality of multi level conductors on the substrate in electrical communication with the first contacts and embedded in a plurality of insulating layers; and

a tape bonded to the interconnect and to the base for electrically connecting the first contacts to the terminal contacts.

8. The temporary package of claim 7 wherein the tape comprises a TAB tape.

9. The temporary package of claim 7 wherein each indentation comprises at least one projection.

10. The temporary package of claim 7 wherein the conductors comprise a plurality of pads and the tape comprises a plurality of second bumps bonded to the pads.

11. A method for testing a semiconductor die or a semiconductor package having bumped contacts comprising:

providing a test circuitry;

providing a temporary package for packaging the die or the package, the temporary package comprising a plurality of terminal contacts in electrical communication with a plurality of conductive traces;

providing an interconnect comprising a substrate, a plurality of first contacts on the substrate, a plurality of multi level conductors embedded in a plurality of insulating layers on the substrate, the first contacts comprising indentations and conductive layers thereon configured to retain and electrically engage the bumped contacts;

placing the interconnect on the temporary package and bonding a tape to the conductors and to the conductive traces to establish electrical communication therebetween;

assembling the die or the package in the temporary package with the first contacts in electrical communication with the bumped contacts and the terminal contacts in electrical communication with the test circuitry; and

applying test signals through the terminal contacts, the first contacts, and the bumped contacts to the die or the package.

12. The method of claim 11 wherein the tape comprises a TAB tape.
 Description Submit all comments and votes
 


FIELD OF THE INVENTION

This invention relates generally to semiconductor manufacture and more particularly to a high speed temporary package and interconnect for testing semiconductor dice, to a method for testing dice using the interconnect, and to a method for fabricating the interconnect.

BACKGROUND OF THE INVENTION

Semiconductor dice must be tested during the manufacturing process to evaluate various electrical parameters of the integrated circuits formed on the dice. Accordingly, different testing procedures have been developed by semiconductor manufacturers for testing semiconductor dice. Standard tests for gross functionality are typically performed by probe testing the dice at the wafer level using probe cards and wafer steppers. Burn-in testing is typically performed after the dice have been singulated and packaged using a burn-in oven or similar testing apparatus in electrical communication with test circuitry. Among the tests performed are dynamic burn-in, input/output leakage, speed verification, opens, shorts, refresh and a range of algorithms to verify AC parameters.

In the case of unpackaged dice, marketed by manufacturers as known good dice (KGD), temporary packages are required to house a single bare die for burn-in and other test procedures. This type of temporary package is described in U.S. Pat. Nos. 5,541,525, 5,519,332 and 5,495,179 to Wood et al.

These temporary packages typically include an interconnect component for establishing temporary electrical communication with the die. The interconnect can include a substrate with contact members for electrically contacting the bond pads or other contact locations on the die. The interconnect can also include conductors, such as metallized traces, for providing a conductive path from testing circuitry to the contact members. Interconnects for temporary packages are disclosed in U.S. Pat. Nos. 5,483,741 and 5,523,697 to Farnworth et al., incorporated herein by reference.

With advances in the architecture of semiconductor devices, it is advantageous to perform some testing of integrated circuits using very high speed testing signals. For example, testing frequencies of 500 MHz and greater are anticipated for some memory products such as DRAMS. The temporary packages and interconnects used to test dice must be capable of transmitting signals at these high speeds without generating parasitic inductance and cross coupling (i.e., "cross talk").

Parasitic inductance and cross coupling can arise in various electrical components of the temporary packages and in the electrical interface of the interconnect with the temporary package. This can adversely effect the test procedure by causing the power supply voltage to drop or modulate during the test procedure and by causing noise and spurious signals.

For example, the conductors on the interconnect are typically wire bonded to corresponding conductive traces and terminal contacts formed on the temporary package. Capacitive coupling can occur between adjacent conductors on the interconnect and between adjacent bond wires to the conductors. High speed switching of the voltage levels in the conductors and bond wires can result in corresponding inadvertent changes in the voltage levels on nearby conductors, or bond wires, resulting in logic errors.

The problems of parasitic inductance and cross coupling can be compounded by the large number of bond pads contained on later generations of semiconductor dice. A large number of bond pads requires a corresponding large number of contact members and conductors on the interconnect. Because of their high density, it can be difficult to locate and construct the contact members and conductors without forming parasitic inductors and initiating cross talk and interconductor noise.

Because of these and other problems, there is a need in the art for improved temporary packages and interconnects for testing semiconductor dice and improved high speed testing methods.

SUMMARY OF THE INVENTION

In accordance with the invention, an improved temporary package and interconnect for testing semiconductor dice are provided. The temporary package comprises a base for retaining a single bare die and a force applying member for biasing the die against the interconnect. The interconnect mounts to the base and includes dense arrays of contact members and multi level conductors in electrical communication with the contact members. Insulating layers can be formed between adjacent levels of conductors to prevent cross talk and capacitive coupling between the conductors. Additionally, if desired, the condu