Method and apparatus for storage of test results within an integrated circuit

Claims

What is claimed is:

1. An integrated circuit comprising:

a plurality of nonvolatile memory elements each capable of storing one of at least two logic states; wherein each of said nonvolatile memory elements stores a state which is dependent upon a result of a test step that is a portion of a sequentially applied performance test; the performance test determining the substantial functionality of the integrated circuit.

2. The integrated circuit of claim 1, further comprising an array of volatile memory elements.

3. The integrated circuit of claim 1, wherein said plurality of nonvolatile memory elements comprises an antifuse.

4. The integrated circuit of claim 1, wherein two of said nonvolatile memory elements store the result of one test step of the sequentially applied performance test.

5. An integrated circuit comprising:

a plurality of nonvolatile memory elements each of which maintains a state which is representative of a pass/fail result of a test step that is a portion of a sequentially applied test performed as part of a production process, the test step determining the substantial functionality of the portion of the integrated circuit subjected to the test.

6. The integrated circuit of claim 5, wherein said plurality of nonvolatile memory elements comprises a laser fuse.

7. An integrated circuit comprising:

a plurality of nonvolatile memory elements which store one of a plurality of possible test step results of a sequentially applied test performed in the process of determining the substantial functionality of the integrated circuit.

8. The integrated circuit of claim 7, wherein the one test step result represents a bin number test result.

9. A Dynamic Random Access Memory device comprising:

a plurality of nonvolatile memory elements each of which maintains a data value which represents a result of a test step that is a portion of a sequentially applied performance test performed on the Dynamic Random Access Memory device, the performance test determining the substantial functionality of the device.

10. The Dynamic Random Access Memory device of claim 9, further comprising a second plurality of nonvolatile memory elements which are coupled to a plurality of redundant memory elements.

11. The Dynamic Random Access Memory device of claim 10, wherein said second plurality of nonvolatile memory elements comprises an antifuse.

12. The Dynamic Random Access Memory device of claim 9, wherein at least a portion of said nonvolatile memory elements are antifuses which are programmed after the Dynamic Random Access Memory device is packaged.

13. A system comprising:

an integrated circuit which comprises a plurality of nonvolatile memory elements each capable of storing a binary logic state, wherein each of said nonvolatile memory elements stores a state which is dependent upon a result of a test step that is a portion of a sequentially applied performance test; the performance test determining the substantial functionality of the integrated circuit.

14. The system of claim 13, wherein said integrated circuit is a microprocessor.

15. The system of claim 13, wherein said integrated circuit is a memory device.

16. A memory module comprising:

an integrated circuit comprising a plurality of nonvolatile memory elements each capable of storing one of at least two logic states wherein each of said nonvolatile memory elements stores a state which is dependent upon a result of a test step that is a portion of a sequentially applied performance test; the performance test determining the substantial functionality of the integrated circuit.

17. The memory module of claim 16, wherein the memory module is a Dual In Line Memory Module.

18. The memory module of claim 16, wherein said integrated circuit is a FLASH memory device.

19. The memory module of claim 16, wherein said integrated circuit is a Dynamic Random Access Memory device and said nonvolatile memory elements are comprised of antifuse circuits.

20. An integrated circuit, comprising:

a substrate;

a plurality of conductive layers disposed on the substrate; and

a read-only storage element having two electrically intercoupled storage sections that are each disposed in a different one of two of the layers and that each have a respective conductivity, a logic state that is stored in the read-only storage element being identified by the respective conductivities of the storage sections, the conductivities resulting either from an electrically closed path through the storage sections, or an electrically opened path through the storage sections, the state having been stored in the read-only storage element during the manufacture of the integrated circuit, the state describing a process used to manufacture the integrated circuit.

21. The integrated circuit of claim 20 wherein said storage sections are serially intercoupled.

22. The integrated circuit of claim 20 wherein the state describes a process step that formed a portion of the integrated circuit.

23. The integrated circuit of claim 20 wherein the state describes a result of a process step that tested the integrated circuit.

24. A semiconductor device, comprising:

a substrate;

multiple conductive layers disposed on the substrate; and

a read-only storage module that includes multiple read-only storage elements that are electrically intercoupled in parallel, each read-only storage element including multiple read-only storage links that are electrically and serially intercoupled and that each have a respective conductivity, a logic state that is stored in the read-only storage module being identified by the respective conductivities of the storage links, the conductivities resulting either from an electrically closed path through the storage links, or an electrically opened path through the storage links, the state having been stored in the read-only storage module during the manufacture of the semiconductor device, the state describing a process used to manufacture the semiconductor device.

25. The semiconductor device of claim 24 wherein each read-only storage link of each the read-only storage elements is disposed in a different one of the layers such that the stored state can be changed by changing the conductivity of one or more of the storage links in only one of the layers during the formation of the only one layer.

26. The semiconductor device of claim 24 wherein one of the read-only storage elements is electrically closed, and remaining ones of the read-only storage elements are electrically opened.

27. The semiconductor device of claim 24 wherein:

the read-only storage module includes at least three read-only storage elements;

two or more of the read-only storage elements each include a single, electrically opened read-only storage link; and

each of the layers includes at most one electrically opened read-only storage link.

28. The semiconductor device of claim 24, further comprising one or more vias that serially intercouple the respective read-only storage links of each read-only storage element.

29. An integrated device, comprising:

a substrate;

a conductive layer formed on the substrate; and

one or more read-only storage elements disposed in the conductive layer, each of the storage elements formed in a respective predetermined logic state during the manufacture of the integrated device, the logic state resulting either from an electrically closed path through the storage elements, or an electrically opened path through the storage elements, and wherein the states of the storage elements collectively describe a process used to manufacture the integrated circuit.

30. A semiconductor structure, comprising:

a substrate;

a first plurality of conductive layers disposed on the substrate; and

a second plurality of read-only storage elements disposed in the conductive layers, each conductive layer having disposed therein at least a respective one of the storage elements, a logic state having been stored in the respective storage element during the manufacture of the semiconductor structure, the logic state resulting either from an electrically closed path through the storage elements, or an electrically opened path through the storage elements, and wherein the state describes a portion of a process used to manufacture the semiconductor structure, the portion of the process having occurred before or during the formation of the conductive layer in which the respective storage element is disposed.

31. The semiconductor structure of claim 30 wherein each conductive layer has disposed therein more than one of the storage elements.

32. The semiconductor structure of claim 30 wherein the first plurality equals the second plurality.

33. The semiconductor structure of claim 30 wherein the state describes a process step that formed a portion of the integrated circuit.

34. The semiconductor structure of claim 30 wherein the state describes a result of a process step that tested the integrated circuit.

35. An integrated circuit, comprising:

a substrate;

a plurality of conductive layers disposed on the substrate; and

a read-only storage element having two electrically intercoupled storage sections that are each disposed in a different one of two of the layers and that each have a conductivity, a logic state that is stored in the read-only storage element being identified by either an electrically closed path through the storage elements, or an electrically opened path through the storage elements, the state having been used to control a manufacturing flow during the manufacture of the integrated circuit.

36. The integrated circuit of claim 34 wherein the stored state caused a predetermined process step to be performed during the manufacture of the integrated circuit, the process step having formed a part of the integrated circuit.

37. The integrated circuit of claim 34 wherein the stored state caused a predetermined process step to be omitted during the manufacture of the integrated circuit.

38. The integrated circuit of claim 34 wherein the stored state caused a predetermined process step to be performed during the manufacture of the integrated circuit, the process step having been a test of the integrated circuit.

39. A semiconductor device, comprising:

a substrate;

multiple conductive layers disposed on the substrate; and

a read-only storage module that includes multiple read-only storage elements that are electrically intercoupled in parallel, each read-only storage element including multiple read-only storage links that are electrically and serially intercoupled and that each have a respective conductivity, a logic state that is stored in the read-only storage module being identified by either an electrically closed path through the storage elements, or an electrically opened path through the storage elements, the state having been used to control a manufacturing flow during the manufacture of the semiconductor device.

40. The semiconductor device of claim 34 wherein each read-only storage link of each the read-only storage elements is disposed in a different one of the layers such that the stored state can be changed by changing the conductivity of one or more of the storage links in only one of the layers during the manufacture of the only one layer.

41. An integrated device, comprising:

a substrate;

a conductive layer disposed on the substrate; and

one or more read-only storage elements disposed in the conductive layer, each of the storage elements formed in a respective predetermined logic state during the manufacture of the integrated device, the logic state resulting either from an electrically closed path through the storage elements, or an electrically opened path through the storage elements, and wherein the states of the storage elements having been used together to control a manufacturing flow during the manufacture of the integrated device.

42. The integrated device of claim 41 wherein the stored states together identify a characteristic of the integrated device.

43. A semiconductor structure, comprising:

a substrate;

a first plurality of conductive layers disposed on the substrate; and

a second plurality of read-only storage elements disposed in the conductive layers, each conductive layer having disposed therein at least a respective one of the storage elements, the respective storage element storing a logic state that was used to control a manufacturing flow during the manufacture of the semiconductor structure and before or during the formation of the conductive layer in which the respective storage element is disposed, wherein the logic state results either from an electrically closed path through the storage elements, or an electrically opened path through the storage elements.

44. An electronic system, comprising:

a data input device;

a data output device; and

computing circuitry coupled to the data input and output devices, the computing circuitry including a memory device that includes,

a substrate,

a plurality of conductive layers formed on the substrate, and

a fuse read-only storage element having two electrically intercoupled storage sections that are each disposed in a different one of two of the layers and that each have a respective conductivity, a logic state that is stored in the read-only storage element being identified by either an electrically closed path through the storage elements, or an electrically opened path through the storage elements, the state having been stored in the read-only storage element during the manufacture of the memory device, the state describing a process used to manufacture the memory device.

45. The electronic system of claim 44 wherein the storage sections are serially intercoupled.

46. The electronic system of claim 44 wherein at least one of the layers comprises polysilicon.

47. The electronic system of claim 44 wherein at least one of the layers comprises a metal.

48. An electronic system, comprising:

a data input device;

a data output device; and

computing circuitry coupled to the data input and output devices, the computing circuitry including a memory device that includes,

a substrate,

a conductive layer disposed on the substrate, and

one or more read-only storage elements disposed in the conductive layer, each of the storage elements formed in a respective predetermined logic state during the manufacture of the memory device, the logic state resulting from either an electrically closed path through the storage elements, or an electrically opened path through the storage elements, the states of the storage elements collectively describing a process used to manufacture the memory device.

49. The electronic system of claim 48 wherein the memory device further comprises a plurality of conductive layers disposed on the substrate, each conductive layer having disposed therein one or more read-only storage elements, each of the storage elements formed in a respective predetermined logic state during the manufacture of the memory device, the states of the storage elements collectively describing a process used to manufacture the memory device.

50. An electronic system, comprising:

a data input device;

a data output device; and

computing circuitry coupled to the data input and output devices, the computing circuitry including a memory device that includes,

a substrate,

a conductive layer disposed on the substrate, and

one or more read-only storage elements disposed in the conductive layer, each of the storage elements formed in a respective predetermined logic state during the manufacture of the memory device, the logic state resulting from either an electrically closed path through the storage elements, or an electrically opened path through the storage elements, the states of the storage elements having been used together to control a manufacturing flow during the manufacture of the memory device.

51. An electronic system, comprising:

a data input device;

a data output device; and

computing circuitry coupled to the data input and output devices, the computing circuitry including a memory device that includes,

a substrate,

a plurality of conductive layers disposed on the substrate, and

a fuse read-only storage element having two electrically intercoupled storage sections that are each disposed in a different one of two of the layers and that each have a respective conductivity, a logic state that is stored in the read-only storage element being identified by either an electrically closed path through the storage elements, or an electrically opened path through the storage elements, the state having been used to control a manufacturing flow during the manufacture of the memory device.

FIELD OF THE INVENTION

This invention relates to integrated circuit test circuits and methods. The invention is particularly related to semiconductor memory devices having internal test circuits, and methods of testing semiconductor memory devices.

BACKGROUND OF THE INVENTION

Semiconductor integrated circuit devices are manufactured on a thin wafer of semiconductor material. Generally many devices are manufactured on a single wafer. These devices may be tested with electrical probes to verify functionality of the devices prior to singulation and/or packaging of individual devices. After a device is packaged, further tests are performed. Devices which do not receive a conventional device package may be tested in a temporary package or die holder, and later shipped in die form. Devices which are shipped in die form after passing a complete test flow may be termed Known Good Die (KGD). Some electrical tests may be performed in a Burn-In oven to weed out parts that would likely fail within a short period of time after being sold if the Burn-In step was not performed. In addition to Probe and Burn-In, parts may be tested both hot and cold to verify functionality over specified environmental conditions.

A complete test flow will often require that parts move from one piece of test equipment to another. A first piece of test equipment and test fixtures may be utilized for Probe, another for Burn-In, and yet another for packaged part testing after Burn-In. After being tested on a particular piece of test equipment, the parts may be sorted into bins according to the test results. Occasionally a part may be misbinned i.e., placed in an incorrect bin. This may occur as a result of machine malfunction, or human error. A failed part that is incorrectly placed in a passing bin has the potential of completing the test flow without further failures and may then be sold as a fully functional part.

SUMMARY OF THE INVENTION

An integrated circuit device has nonvolatile memory elements which are programmed to reflect successful completion of a test or series of tests, or completion of a formation step or a series of formation steps of a semiconductor process. Prior to peforming additional tests, the nonvolatile memory element corresponding to successful completion of a previous test is read to verify that the part has indeed successfully completed the previous test. The nonvolatile memory elements may also be read prior to performing other production related activities such as packaging the device, and performing quality assurance checks. The nonvolatile memory elements may also be read prior to sale of the devices, and in the event that a device is returned from a customer. The integrated circuit may be a memory device such as a Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Video Random Access Memory (VRAM), etc. The invention is also applicable to other types of integrated circuit devices such as microprocessors, microcontrollers, memory controllers, Application Specific Integrated Circuits (ASICs), etc. Generally, any integrated circuit which requires multiple test steps and in which a nonvolatile memory element can be incorporated without prohibitively increasing the device manufacturing cost is a candidate for incorporation of the invention.

Large volumes of data may be recorded in the process of testing a single integrated circuit device. It is not feasible to store all of this information on the device itself. In accordance with the present invention, an antifuses is blown at predetermined test milestones to record a successful completion of tests associated with the milestone. Devices which do not successfully pass the tests do not have the fuse blown. Subsequent testing of each memory chip proceeds after verification of the blown fuse indicating that the device has passed previous test procedures. Memory devices which do not pass the tests or which do not have the fuse blown are removed from the test flow.

In an alternate embodiment of the present invention, multiple fuses are used to store information concerning the results of a test process. For example, three nonvolatile memory elements may be used to store one of eight bin numbers each of which represent a part classification based on the test results.

Nonvolatile memory elements associated with test results may be used by customers as part of their incoming inspection process. The data stored in these elements may represent standard test results, or results of tests that are specific to the customer.

After initial testing, devices which pass the tests are sent to a memory device assembly area to be packaged. Some devices may not require packaging as they may be destined to be shipped in die form as Known Good Die (KGD) devices.

Prior to encapsulation, nonvolatile memory elements may be read to verify that previous test sequences have been successfully completed. After packaging, the memory devices are tested further. Device Burn-in and other test procedures are performed to verify functionality of the devices after packaging and in adverse environmental conditions. These tests are also useful in detecting devices which are subject to infant mortality. In a preferred embodiment of the invention, devices which pass some or all of these remaining tests have antifuses which are associated with post packaging test milestones. These antifuses are programmed by application of electrical signals to device inputs and/or outputs. As a final inspection prior to shipping the devices, all appropriate fuses may be read to verify successful completion of all test procedures. While certain test procedures are described such as probe testing, Burn-In, etc., it should be noted that the invention is not limited to test flows which utilize these procedures. Alternate test flows in which some or all of these tests are not performed, in which additional tests are performed, or in which multiple tests are combined into a single test are equally valid. Furthermore, nonvolatile memory elements other than antifuses may be used to store the test or formation data.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the invention as well as objects and advantages will be best understood by reference to the appended claims, detailed description of particular embodiments and the accompanying drawings where:

FIG. 1 is a block schematic diagram of a computer system.

FIG. 2 is a front view and pin assignment of a memory module.

FIG. 3 is a schematic diagram of a memory device.

FIG. 4 is a schematic diagram of an antifuse circuit.

FIG. 5 is a flow chart of a test process.

FIG. 6 is a block diagram of a semiconductor device that incorporates a nonvolatile storage element in accordance with an embodiment of the present invention.

FIG. 7 is a top plan view of one embodiment of the storage-element bank of FIG. 6 with portions broken away.

FIG. 8 is a layout diagram of a portion of another embodiment of the storage-element bank of FIG. 6.

FIG. 9 is a side view of the portion of the storage-element bank of FIG. 8 taken along lines 9--9.

FIG. 10 is a schematic diagram of yet another embodiment of the storage-element bank of FIG. 6.

FIG. 11 is a layout diagram of the storage-element bank of FIG. 10.

FIG. 12 is a block diagram of an electronic system that incorporates a memory device formed in accordance with an embodiment of the present invention.

DESCRIPTION OF THE INVENTION

A computer system 10 as shown in FIG. 1 has a microprocessor 12 which is coupled to a memory module 14 by control circuit 16 and a data bus 18. Memory module 14 may be, but is not limited to, being a removable module such as a Dual In-Line Memory Module (DIMM), a Single In-Line Memory Module (SIMM), or Multi-Chip Module (MCM). Alternatively, the memory module 14 may be a memory circuit which is directly coupled to the system such as a fast SRAM cache. Control circuit 16 receives microprocessor address and control signals 20 from the microprocessor 12 and sends memory module address and control signals 22 to memory module 14. Video information may be sent to display 24 via signals 26 from control circuit 16.

FIG. 2 is a front view and pin assignment of a DIMM which may be representative of the memory module 14 of FIG. 1. The DIMM module 14 of FIG. 2 is made up of a plurality of memory devices 22 which are mounted on a printed circuit board 24. Data stored in the DIMM is accessible to the microprocessor 12 of FIG. 1 through connector 26. Address and control signals may be buffered through buffer 28 to reduce loading on these signals. Additional information concerning DIMM 14 as well as alternate memory modules may be found in the MICRON TECHNOLOGY INC. 1995 DRAM DATA BOOK, herein incorporated by reference.

FIG. 3 is a block schematic diagram of a DRAM which may be representative of one of the memory devices 22 of FIG. 2. The DRAM of FIG. 2 may be any one of a wide variety which are currently available, and others which will become available as new memory devices are developed and manufactured. Within memory device 22, are a plurality of nonvolatile memory elements 32. The nonvolatile memory elements may be laser fuses, electrical fuses, antifuses, or a combination thereof. Alternatively, the nonvolatile memory elements may be FLASH memory cells, FERAM memory cells, or any other nonvolatile type of memory cell. The preferred type of nonvolatile memory cell will depend largely on the integrated circuit device type and the process used to fabricate the integrated circuit. In a preferred embodiment of the present invention, the memory device is a DRAM, and the nonvolatile memory elements are electrically programmable antifuses. The use of nonvolatile memory elements within DRAMs is well known in the industry. Laser fuses for example, have been widely used for enabling redundant memory elements to replace nonfunctional elements within DRAM devices.

Nonvolatile memory elements 32 receive address 34, data 36 and control 38 inputs either directly or through control circuitry such as DRAM control circuit 40 and data path control circuit 42. These inputs may be used to program and/or read the nonvolatile memory elements. Outputs of the nonvolatile memory elements are used to enable redundant memory elements 44 and may also be read out of the device over data input/output lines 36. Memory device 22 is primarily used for data storage in memory array 46 in which individual elements or groups of elements are addressed by address 34 through addressing circuitry 48.

FIG. 4 is a schematic diagram of an antifuse circuit 50 which may be used as a single nonvolatile memory element which may be utilized to store test result information in an integrated circuit such as the memory device 22 of FIG. 2. In one embodiment of the present invention, a plurality of antifuse nonvolatile memory elements 50 along with control circuitry, not shown, will make up the nonvolatile memory element circuit 32 of FIG. 3.

Antifuse element 52 is manufactured in a manner which is similar to the manufacture of a capacitor. An unblown antifuse has two electrodes separated by a dielectric. If the antifuse element remains unprogrammed, there is no current path through the element. To program the antifuse, input PGND on signal node 54 is elevated to a programming potential, and signal PROG 56 is taken to a logic high potential. While signal 56 is high, device 58 will provide a path to ground through device 60 to node 62. The potential difference between the programming potential and ground is sufficient to cause the dielectric of the antifuse structure to break down and the two nodes 54 and 62 become shorted together. Thus, when programmed, a current path does exist between nodes 54 and 62. The antifuse is a binary signal storage device since a binary logic level can be associated with the blown and unblown states of the anti fuse through the presence or absence of a current path through the device. After programming selected devices, the PGND signal 54 and the PROG signal 56 are both coupled to logic low potentials. While PROG is at a logic low potential, inverter 64 activates device 66 which provides a path for a logic low level at node 62 to be coupled to node 68 if antifuse 52 is conductive. To read the antifuse, signal READ* 70 is coupled to a logic low potential which turns on device 72. Device 72 couples a high potential from Vcc node 73 through a resistive device 74 to node 68. If the antifuse is conductive, node 68 will remain low since device 74 is designed to be more resistive than the programmed antifuse. If the antifuse is not blown (nonconductive), node 68 will go high. Output node 78 will be driven to the opposite state of node 68 by inverter 76. If antifuse 52 is blown, a low potential will remain at node 68, and node 78 will remain high. If the antifuse is unblown, node 68 will go high when the antifuse is read, node 78 will go low and device 80 will be turned on to provide a path from Vcc to node 68 through resistive device 74. Device 80 is used to latch the high level logic state at node 68 after the READ* signal is brought back high after a read function. If the READ* is not brought back high after the read function, a DC current path from Vcc to ground may exist through a blown antifuse.

Programming signals READ* 70, PROG and PGND may be logically derived through the use of a test sequence of control signals such as a Write-CAS-Before-RAS (WCBR) programming cycle in a DRAM, the use of a super voltage signal, or other methods of performing test functions within an integrated circuit. The programming potential may be applied to a device input, or may be internally generated through the use of a charge pump circuit.

Laser fuses may be programmed through the use of a laser. In nonvolatile memory devices such as FLASH memory devices, a number of memory elements of the array of memory elements may be utilized to store the test information. For example, a piece of test equipment may read a set of bits representing test results from a predetermined memory location, perform a test of the memory device and then rewrite the test results back into a predetermined location. The test results that are written back into the device may be updated to reflect the results of the most current test. Since this data would be lost when the device is erased, it is not as desirable as adding a number of dedicated nonvolatile memory elements which may be