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Claims  |
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What is claimed is:
1. A semiconductor device formed on a wafer, comprising:
a semiconductor memory circuit; and
a test circuit for testing the semiconductor memory circuit;
wherein said semiconductor memory circuit includes a plurality of memory cells disposed in the form of a matrix having rows and columns for respectively storing data therein, and is activated based on a test pattern so as to generate the data
stored in the respective memory cells for every column as output data; and
wherein said test unit includes:
a test pattern generator, which generates said test pattern indicative of a type of test to be performed and an expected value to be obtained by testing according to the test pattern, in response to a received command;
a decision unit, which compares the output data with the expected value and generates a result of the comparison; and
a translation unit, which converts the result of the comparison into address data and generates the address data.
2. A semiconductor device as claimed in claim 1, wherein said semiconductor memory circuit comprises
bit lines to which the output data are provided;
sense amplifiers for amplifying the output data provided to said bit lines; and
column switches connected between said bit lines and a pair of data buses, said sense amplifiers and said column switches being respectively controlled based on column signals supplied by column lines arranged in a direction of said columns.
3. A semiconductor device as claimed in claim 1, wherein:
said decision unit comprises a plurality of decision circuits equal in number to a number of said columns and respectively associated with said columns; and
said translation unit comprises
a plurality of flag circuits respectively corresponding to said plurality of decision circuits, and
a plurality of translation circuits respectively corresponding to said plurality of flag circuits, each said flag circuit being brought to a first state when the result of the comparison generated by said corresponding decision circuit is normal
and being brought to a second state when the result of the comparison is abnormal, and each said translation circuit storing therein an address for a memory cell from which data indicative of an abnormal condition has been received, when said flag
circuit is placed in the second state and providing the address to said test circuit.
4. A semiconductor device as claimed in claim 3, wherein said translation unit further includes a plurality of buffer circuits, which respectively successively store therein addresses provided by said translation circuits and thereafter
sequentially providing the stored addresses to said test circuit.
5. A semiconductor device as claimed in claim 1, wherein:
said decision unit comprises a plurality of decision circuits equal in number to a number of said columns and respectively associated with said columns; and
said translation unit comprises
a plurality of sequentially-connected translation circuits respectively corresponding to said plurality of decision circuits, and
a plurality of handshake control circuits respectively corresponding to said translation circuits, each said translation circuit storing therein an address for a memory cell from which data indicative of an abnormal condition has been provided,
when the result of the comparison generated by said corresponding decision circuit is abnormal, and each said handshake control circuit detecting a state of a next-stage handshake control circuit, providing said address stored in said corresponding
translation circuit to a next-stage translation circuit when the next-stage handshake control circuit is placed in a first state, and holding said address stored in said corresponding translation circuit when the next-stage handshake control is placed in
a second state.
6. A semiconductor device as claimed in claim 5, wherein said handshake control circuit comprises
a first inverter having an input for receiving a first control signal;
a first transfer gate circuit, electrically connected between a first input terminal that is electrically connected to said decision circuit, and a first node, and having
a first N channel MOS transistor having a gate electrode for receiving the first control signal, and
a first P channel MOS transistor having a gate electrode that is electrically connected to an output of the first inverter;
a second transfer gate circuit, electrically connected between a second input terminal and the first node, and having
a second N channel MOS transistor having a gate electrode that is electrically connected to the output of the first inverter, and
a second P channel MOS transistor having a gate electrode for receiving the first control signal;
a third N channel MOS transistor having a drain electrode that is electrically connected to the first node and having source and gate electrodes for respectively receiving a ground potential and an initialization signal;
a first C element circuit having .alpha., .beta. and .gamma. terminals that are respectively electrically connected to the first node, a third input terminal, and a second node;
a second C element circuit having .alpha., .beta. and .gamma. terminals that are respectively electrically connected to the second node, a fourth input terminal, and a first output terminal;
a fourth N channel MOS transistor having a drain electrode that is electrically connected to the second node and having source and gate electrodes for respectively receiving the ground potential and the initialization signal;
a second output terminal electrically connected to the first node; and
a third output terminal electrically connected to the second node.
7. A semiconductor device as claimed in claim 6, wherein each of said first and second C element circuits comprises
third and fourth P channel MOS transistors that are electrically series connected between a source potential and a third node;
fifth and sixth N channel MOS transistors that are electrically series connected between the third node and the ground potential;
a second inverter that is electrically connected between the third node and the .gamma. terminal; and
a third inverter that is electrically connected between gate electrodes of the third P channel MOS transistor and the sixth N channel MOS transistor, and the .beta. terminal; and wherein the .alpha. terminal is electrically connected to the
gate electrodes of the fourth P channel MOS transistor and the fifth N channel MOS transistor.
8. A semiconductor device as claimed in claim 5, wherein said handshake control circuit comprises
a first inverter having an input for receiving a first control signal;
a first transfer gate circuit, electrically connected between a first input terminal that is electrically connected to said decision circuit, and a second input terminal, and having
a first N channel MOS transistor having a gate electrode for receiving the first control signal, and
a first P channel MOS transistor having a gate electrode that is electrically connected to the output of the first inverter;
a second P channel MOS transistor having drain and source electrodes that are respectively electrically connected to the second input terminal and a source potential, and having a gate electrode for receiving an initialization signal;
a second inverter having an input and an output that are respectively electrically connected to the second input terminal and a first node;
a first C element circuit having .alpha., .beta. and .gamma. terminals that are respectively electrically connected to the first node, a third input terminal and a second node, a .delta. terminal for receiving the first control signal, and an
.eta. terminal that is electrically connected to the output of said first inverter;
a third inverter having an input and output that are respectively electrically connected to the second node and a third node;
a second C element circuit having .alpha., .beta. and .gamma. terminals that are respectively electrically connected to the third node, a fourth input terminal and a first output terminal, a .delta. terminal for receiving the first control
signal, and an .eta. terminal that is electrically connected to the output of said first inverter; and
a third P channel MOS transistor having drain and source electrodes that are respectively electrically connected to the second node and the source potential and having a gate electrode for receiving the initialization signal.
9. A semiconductor device as claimed in claim 8, wherein each of said first and second C element circuits comprises
fourth through sixth P channel MOS transistors that are electrically series-connected between the source potential and a fourth node;
second through fourth N channel MOS transistors that are electrically series-connected between the fourth node and a ground potential; and
a fourth inverter electrically connected between gate electrodes of said fifth P channel MOS transistor and said third N channel MOS transistor, and the .beta. terminal, wherein the .alpha. terminal is electrically connected to gate electrodes
of said sixth P channel MOS transistor and said second N channel MOS transistor, the .delta. terminal is electrically connected to a gate electrode of said fourth P channel MOS transistor, and the .eta. terminal is electrically connected to a gate
electrode of said fourth N channel MOS transistor.
10. A semiconductor device as claimed in claim 5, wherein each said handshake control circuit comprises
a first inverter having an input for receiving a first control signal;
a first transfer gate circuit, electrically connected between a first input terminal that is electrically connected to said decision circuit, and a second input terminal, and having
a first N channel MOS transistor having a gate electrode for receiving the first control signal, and
a first P channel MOS transistor having a gate electrode that is electrically connected to the output of the first inverter;
a second P channel MOS transistor having drain and source electrodes that are respectively electrically connected to the second input terminal and a source potential and having a gate electrode for receiving an initialization signal;
a second inverter having an input and an output that are respectively electrically connected to the second input terminal and a first node;
a first C element circuit having .alpha., .beta., and .gamma. terminals that are respectively electrically connected to the first node, a third input terminal, and a second node, and an .eta. terminal that is electrically connected to the
output of said first inverter;
a second inverter having an input and an output that are respectively electrically connected to the second node and a third node;
a second C element circuit having .alpha., .beta., and .gamma. terminals that are respectively electrically connected to the third node, a fourth input terminal, and a first output terminal, and an .eta. terminal that is electrically connected
to the output of said first inverter; and
a third P channel MOS transistor having drain and source electrodes that are respectively electrically connected to the second node and the source potential and having a gate electrode for receiving the initialization signal.
11. A semiconductor device as claimed in claim 10, wherein each of said first and second C element circuits comprises
fourth and fifth P channel MOS transistors that are electrically series-connected between the source potential and a fourth node;
second through fourth N channel MOS transistors that are electrically series connected between the fourth node and a ground potential; and
a fourth inverter electrically connected between gate electrodes of said fourth P channel MOS transistor and said third N channel MOS transistor, and the .beta. terminal, wherein the .alpha. terminal is electrically connected to gate electrodes
of said fifth P channel MOS transistor and said second N channel MOS transistor, and the .eta. terminal is electrically connected to a gate electrode of said fourth N channel MOS transistor.
12. A semiconductor device as claimed in claim 1, formed on a semiconductor wafer, wherein a semiconductor memory circuit region in which said semiconductor memory circuit is formed and a test management region in which said test pattern
generator, said decision unit and said translation unit are formed, are separated by scribe lines corresponding to cutting estimated regions, and said semiconductor memory circuit, said test pattern generator and said decision unit are electrically
connected to one another by connecting means including a plurality of conductor layers formed on the scribe lines.
13. A semiconductor device as claimed in claim 12, wherein the conductor layers of said connecting means are respectively connected to said semiconductor memory circuit, said test pattern generator and wiring layers of said decision unit by
contact means at positions spaced away from the scribe lines, and each said contact means is covered with an insulating layer so as to avoid exposure to the scribe lines.
14. A semiconductor device as claimed in claim 13, wherein said test management region is divided into a first test management region and a second test management region, both of which are disposed in opposing relationship with said
semiconductor memory circuit region interposed therebetween.
15. A semiconductor device as claimed in claim 1, formed on a semiconductor wafer, said semiconductor device including a semiconductor memory circuit region in which said semiconductor memory circuit is formed and a test management region in
which said test pattern generator, said decision unit and said translation unit are formed, said test management region surrounding said semiconductor memory circuit region and being disposed on scribe lines corresponding to cutting estimated regions,
and wherein said semiconductor memory circuit, said test pattern generator and said decision unit are connected to one another by connecting means including a plurality of conductor layers formed on the scribe lines.
16. A semiconductor device as claimed in claim 1, wherein said semiconductor memory circuit includes
bit line pairs respectively connected to the memory cells;
a read circuit for varying the potential on a column according to a change in potential on each said bit line;
a column decoder connected to one end of each said column through a first switch means; and
decision circuits connected to another end of each column through a second switch means, said first and second switch means being respectively brought into non-conduction and conduction upon a test operation so that said read circuit varies the
potential on the column, whereby the potential on the column is compared with the expected value by each said decision circuit.
17. A semiconductor device as claimed in claim 16, further including a plurality of precharge circuits each supplying a source potential to the column, and wherein said read circuit comprises
a first N channel MOS transistor having a drain electrode that is electrically connected to the column line, a source electrode for receiving a first control signal having a potential reduced by a predetermined potential from the source
potential, and a gate electrode that is electrically connected to a first node;
a second N channel MOS transistor having a drain electrode that is electrically connected to a second node, a source electrode that is electrically connected to the first node, and a gate electrode that is electrically connected to one bit line
of said each bit line pair;
a third N channel MOS transistor having a drain electrode that is electrically connected to a third node, a source electrode that is electrically connected to the first node, and a gate electrode that is electrically connected to the other bit
line of said each bit line pair;
a fourth N channel MOS transistor having a drain electrode that is electrically connected to a first read data bus having one of the source potential and the ground potential, a source electrode that is electrically connected to the second node,
and a gate electrode that is electrically connected to the column;
a fifth N channel MOS transistor having a drain electrode that is electrically connected to a second read data bus having the other of the source potential and the ground potential, a source electrode that is electrically connected to the third
node, and a gate electrode that is electrically connected to the column;
a sixth N channel MOS transistor having a drain electrode that is electrically connected to the first node, a source electrode that is electrically connected to the ground potential, and a gate electrode for receiving a second control signal;
and
a precharge circuit for supplying the source potential to the first node.
18. A semiconductor device as claimed in claim 16, further including a plurality of precharge circuits each supplying a source potential to the column and wherein said read circuit comprises
a first N channel MOS transistor having a drain electrode that is electrically connected to the column line, a source electrode that is electrically connected to a first node, and a gate electrode for receiving a first control signal having a
potential higher than the source potential;
a second N channel MOS transistor having a drain electrode that is electrically connected to a second node, a source electrode that is electrically connected to the first node, and a gate electrode that is electrically connected to one bit line
of said each bit line pair;
a third N channel MOS transistor having a drain electrode that is electrically connected to a third node, a source electrode that is electrically connected to the first node, and a gate electrode that is electrically connected to the other bit
line of said each bit line pair;
a fourth N channel MOS transistor having a drain electrode that is electrically connected to a first read data bus having one of the source potential and a ground potential, a source electrode that is electrically connected to the second node,
and a gate electrode that is electrically connected to the column;
a fifth N channel MOS transistor having a drain electrode that is electrically connected to a second read data bus having the other of the source potential and the ground potential, a source electrode that is electrically connected to the third
node, and a gate electrode that is electrically connected to the column; and
a sixth N channel MOS transistor having a drain electrode that is electrically connected to the first node, a source electrode that is electrically connected to the ground potential, and a gate electrode for receiving a second control signal.
19. An integrated device, comprising:
a semiconductor memory circuit, formed as a first internal component of the device; and
a test circuit, formed as a second internal component of the device, for testing the semiconductor memory circuit,
wherein the semiconductor memory circuit includes a plurality of memory cells disposed in the form of a matrix with rows and columns, for respectively storing data therein, and
wherein the test circuit includes:
means for generating, in response to any one of a plurality of commands, one of a plurality of test patterns corresponding to said one command and applying the generated test pattern to the memory cells, wherein the generated test pattern causes
test data to be stored in each of the memory cells and provided as output data of the memory cells corresponding to the generated test pattern;
means for generating a plurality of expected values corresponding to the generated test pattern;
means for comparing the output data of the memory cells corresponding to the generated test pattern with respective expected values corresponding to the generated test pattern and generating a result of the comparison for each of the memory
cells; and
means for generating an address word that corresponds to the location of a defective one of the memory cells, for which the comparison result indicates that the output data is not identical to the respective expected value.
20. For an integrated device comprising an internal semiconductor memory circuit and an internal test circuit for testing the semiconductor memory device, which includes a plurality of memory cells disposed on the device in the form of a matrix
with rows and columns for respectively storing data therein, a method for testing the semiconductor memory circuit, the method comprising:
generating, by the test circuit, in response to any one of a plurality of commands, one of a plurality of test patterns corresponding to said one command and applying the generated test pattern to the memory cells, wherein the generated test
pattern causes test data to be stored in each of the memory cells and provided as output data of the memory cells corresponding to the generated test pattern;
generating, by the test circuit, a plurality of expected values corresponding to the generated test pattern;
comparing, by the test circuit, the output data of the memory cells corresponding to the generated test pattern with respective expected values corresponding to the generated test pattern and generating a result of the comparison for each of the
memory cells; and
generating, by the test circuit, an address word that corresponds to the location of a defective one of the memory cells, for which the comparison result indicates that the output data is not identical to the respective expected value.
21. A semiconductor device comprising a semiconductor memory circuit formed on a wafer, and a test circuit formed on the wafer for testing the semiconductor memory circuit,
said semiconductor memory circuit having a plurality of memory cells disposed in the form of a matrix having rows and columns, for respectively storing data therein, and being activated based on a test pattern so as to generate the data stored in
the respective memory cells for every column as output data,
said test circuit comprising:
a test pattern generator, which generates said test pattern indicative of a type of test to be performed, and an expected value to be obtained by testing according to the test pattern, in response to a received command;
a decision unit, which compares the output data with the expected value and generates a result of the comparison; and
a translation unit, which converts the result of the comparison into address data and generates the address data.
22. A device having a semiconductor memory circuit formed on a wafer, and a test circuit formed on the wafer for testing the semiconductor memory circuit, the semiconductor memory circuit having a plurality of memory cells disposed in the form
of a matrix with rows and columns, for respectively storing data therein, the test circuit comprising:
means for generating, in response to any one of a plurality of commands, one of a plurality of test patterns, corresponding to said one command, and applying the generated test pattern to the memory cells, wherein the generated test pattern
causes test data to be stored in each of the memory cells and provided as output data of the memory cells corresponding to the generated test pattern;
means for generating a plurality of expected values corresponding to the generated test pattern;
means for comparing the output data of the memory cells corresponding to the generated test pattern with respective expected values corresponding to the generated test pattern and generating a result of the comparison for each of the memory
cells; and
means for generating an address word that corresponds to the location of a defective one of the memory cells, for which the comparison result indicates that the output data is not identical to the respective expected value.
23. For a device having a semiconductor memory circuit formed on a wafer and a test circuit formed on the wafer for testing the semiconductor memory circuit, wherein the semiconductor memory circuit has a plurality of memory cells disposed in
the form of a matrix with rows and columns for respectively storing data therein, a method for testing the semiconductor memory circuit, comprising:
generating, by the test circuit, in response to any one of a plurality of commands, one of a plurality of test patterns corresponding to said one command and applying the generated test pattern to the memory cells, wherein the generated test
pattern causes test data to be stored in each of the memory cells and provided as output data of the memory cells corresponding to the generated test pattern;
generating, by the test circuit, a plurality of expected values corresponding to the generated test pattern;
comparing, by the test circuit, the output data of the memory cells corresponding to the generated test pattern with respective expected values corresponding to the generated test pattern and generating a result of the comparison for each of the
memory cells; and
generating, by the test circuit, an address word that corresponds to the location of a defective one of the memory cells, for which the comparison result indicates that the output data is not identical to the respective expected values. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device having a semiconductor memory circuit whose operation is tested in combination with an external test means, a layout of the semiconductor device and a method of testing the semiconductor memory
circuit.
2. Description of the Related Art
A built-in self test (hereinafter called "BIST") has been known as a test on the operation of a semiconductor device. As references about the BIST, there have been disclosed the following ones: (1) "A 45 ns 64 Mb DRAM with a Merged Match-line
Test Architecture", S. Mori et al, IEEE, Dige. of Tech. Papers, P. 110-111, 1991, (2) "Design and Test on Computer", by H. Fujiwara, issued by Engineering book publisher, P204-208, and (3) "55 ns 16 Mb DRAM provided with a Self-Test Function", Koike et
al, Singaku Giho SDM69-39, P79-85, 1999, etc.
Further, "A zero-Overhead Self-Timed 160 ns 546 CMOS Divider" Williams, T. E. et al, ISSCC, Dig. of Tech. Papers, P98-99, 1991 has been disclosed as a reference about a method of controlling a FIFO (First-In First-Out) circuit related to a test.
In the prior art typified by the above-described disclosures, however, since the amount of transfer of data between a semiconductor device and an external test means increases with a great increase in the capacity of a memory portion of a
semiconductor memory circuit, the time required to test the semiconductor memory circuit becomes longer. An increase in the rate of compression of data is also considered as a method of reducing the amount of transfer of the data therebetween. It is
however understood from the result of a test based on compressed data that only the test for making a decision as to whether the compressed data is good or bad for each unit of the compressed data, can be realized. It is thus difficult to specify
positions where defective data are produced. This will exert an influence on the relief of redundancy of the semiconductor memory circuit having large capacity.
Namely, the relief of its redundancy is intended for the improvement in yield by the replacement of a defective memory cell with a spare memory cell for its relief. However, the non-pinpointing or determination of the position of the defective
memory cell will make it difficult to carry out the redundancy relief or will cause needless usage of a memory cell used for the relief of its redundancy because the redundancy relief is performed for each large-scale unit.
SUMMARY OF THE INVENTION
Typical ones of various inventions, which have been made by the inventors of the present application to solve the problem typified above, are shown below. The inventions other than the inventions to be described below will be understood from a
detailed description to be explained later.
Namely, there is provided a semiconductor device having a semiconductor memory circuit whose operation is tested in combination with an external test means, which comprises:
a test pattern generator for generating a test pattern indicative of the type of test and an expected value estimated to be obtained by the test pattern in response to a command issued from the test means;
the semiconductor memory circuit having a plurality of memory cells disposed in the form of a matrix with rows and columns, for respectively storing data therein, and being activated based on the test pattern so as to output the data stored in
the respective memory cells column by column;
a decision unit for comparing each outputted data with the expected value and outputting the result of comparison therefrom; and
a translation unit for converting the result of comparison into address data and outputting it to the external test means.
According to such a construction, since a defective one of the memory cells is specified, it can be efficiently replaced by a spare memory cell in a redundancy relieving process corresponding to a process subsequent to the execution of this
specifying test. Namely, since only the defective memory cell need can be replaced by the spare memory cell during the redundancy relieving process, unnecessary waste of the spare memory cell can be eliminated and the time necessary for its replacement
can be greatly shortened.
A lot of time is normally required upon the redundancy relieving process. Therefore, since the shortening of the time by such a construction contributes to a reduction in cost, the shortening of a period up to the supply of products, etc., a
very great effect can be expected in a semiconductor field. Further, since the test means can be realized by such a simple configuration where only address data indicative of defective portions will be stored, the test means is available at low cost.
BRIEF DESCRIPTION OF THE DRAWINGS
While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further
objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:
FIG. 1 is a circuit block diagram showing a first embodiment of the present invention;
FIG. 2 is a partial circuit block diagram illustrating a second embodiment of the present invention;
FIG. 3 is a partial circuit block diagram depicting a third embodiment of the present invention;
FIG. 4 is a partial circuit block diagram showing the third embodiment of the present invention in detail;
FIG. 5 is a partial circuit block diagram illustrating a fourth embodiment of the present invention;
FIG. 6 is a circuit block diagram depicting a partial configuration of the fourth embodiment in detail;
FIG. 7 is a circuit block diagram showing a fifth embodiment of the present invention;
FIG. 8 is a circuit diagram illustrating a C element circuit employed in the fifth embodiment;
FIG. 9 is a circuit block diagram depicting another modification of the fifth embodiment;
FIG. 10 is a circuit diagram showing a C element circuit employed in the modification shown in FIG. 9;
FIG. 11 is a circuit block diagram illustrating a further modification of the fifth embodiment;
FIG. 12 is a circuit diagram depicting a C element circuit employed in the further modification shown in FIG. 11;
FIG. 13 is a partial layout showing a sixth embodiment of the present invention;
FIG. 14 is a partial circuit block diagram illustrating the sixth embodiment;
FIG. 15 is a circuit block diagram showing the sixth embodiment in detail;
FIG. 16 is a partial timing chart for describing the operation of the sixth embodiment;
FIG. 17 is a partial layout illustrating a seventh embodiment of the present invention;
FIG. 18 is a partially sectional view depicting an eighth embodiment of the present invention;
FIG. 19 is a partial circuit layout illustrating a ninth embodiment of the present invention;
FIG. 20 is a partial circuit layout showing a tenth embodiment of the present invention;
FIG. 21 is a circuit block diagram illustrating the tenth embodiment in detail;
FIG. 22 is a partial layout (pretreating process) showing an eleventh embodiment of the present invention;
FIG. 23 is a partial layout (wafer test process) illustrating the eleventh embodiment;
FIG. 24 is a partial layout (scribe process) showing the eleventh embodiment;
FIG. 25 is a flowchart (classifying process) for describing the eleventh embodiment;
FIG. 26 is a partial circuit block diagram showing a twelfth embodiment of the present invention;
FIG. 27 is a circuit diagram illustrating a determination circuit employed in the twelfth embodiment;
FIG. 28 is a partial circuit block diagram depicting a thirteenth embodiment of the present invention;
FIG. 29 is a partial circuit block diagram showing a fourteenth embodiment of the present invention; and
FIG. 30 is a partial circuit block diagram illustrating a fifteenth embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Preferred embodiments of the invention according to the present application will hereinafter be described with reference to the accompanying drawings. Although typical portions are centrally described as embodiments in the description of various
embodiments to be described later, portions whose descriptions are omitted or portions simplified in description will be easily understood if consideration is given to the descriptions of other embodiments. The accompanying drawings used for their
description are schematically illustrated to help the understanding of the present invention. Elements of structure similar to one another, which are employed in the respective drawings, are identified by the same reference numerals and symbols and the
description of certain common elements will be omitted whenever superfluous.
A first embodiment will first be described with reference to FIG. 1. Only a schematic view of the first embodiment of the present invention is illustrated in FIG. 1. Individual portions will be described in detail with regard to other
embodiments to be explained later.
The semiconductor device 100 is tested for various test items by an externally-provided test means 101. As the test for the items, for example, a test on a decision as to whether the operation of the present semiconductor device 100 is good or
bad or on determination or specification of a defective portion, is considered. Various tests are also considered in addition to this. However, the test items are suitably selected by a test executor. The following respective embodiments respectively
show a case in which a semiconductor device has a semiconductor memory circuit and a test on the semiconductor memory circuit is executed. However, the present invention can be applied to tests for other various semiconductor integrated circuits.
The test means 101 has, for example, the function of generating a test start command corresponding to a command indicative of the initiation or start of a test and performing the final process in response to the result of its test.
The semiconductor device 100 comprises a test pattern generator 102 for generating a test pattern indicative of the type of test, a test command for the designation and control of an address (a control signal with respect to respective portions),
and an expected value defined as the reference for comparison in a determination or decision unit, in response to the test start command sent from the test means 101, a semiconductor memory circuit 103 for performing a test on the holding of data therein
and reading of it therefrom or writing of it thereto based on the test pattern and the test command, the decision unit 104 for performing a comparison between results outputted from the semiconductor memory circuit 103 for every column and the expected
value and outputting the result of comparison therefrom, and a converting or translation unit 105 for converting the result of comparison outputted from the decision unit 104 into an address word and transferring it therefrom.
The operation of the semiconductor device 100 will next be described in brief. When the test start command is outputted from the test means 101, the test pattern generator 102 first generates a test pattern, a test command and an expected value
all programmed in advance in response to the test start command. Thereafter, the test pattern generator 102 supplies the test pattern and the test command to the semiconductor memory circuit 103 and supplies the expected value to the decision unit 104.
The semiconductor memory circuit 103, which has received the test pattern and the test command therein, performs a data write operation and thereafter reads data based on data stored in each memory cell defined in a desired row for each column. The data
read out for each column is compared with the expected value by the decision unit 104. A decision as to whether each memory cell placed in the semiconductor memory circuit 103 is good or bad, can be realized from its comparison. Each result of
comparison is supplied to the converting unit 105 from which an address word indicative of a portion in which a failure or defect has occurred, is generated based on the result of comparison and is thereafter outputted to the test means 101. The test
means 101 stores the outputted address word therein. Since such an operation is effected on all the rows, address words indicative of all the failed portions in the semiconductor memory circuit 103 are stored in the test means 101.
Since each stored address word is used for specifying the faulty portion of each memory cell, the memory cell associated with the address word is efficiently replaced by a spare memory cell during the next redundancy relieving process. Namely,
since only the defective memory cell will be replaced with the spare memory cell during the redundancy relieving process, needless waste of each spare memory cell can be avoided and the time required to replace the defective memory cell with the spare
one can be greatly shortened.
A lot of time is normally required upon the redundancy relieving process. Therefore, since the shortening of the time by the construction of the present embodiment contributes to a reduction in cost, the shortening of a period up to the supply
of products, etc., a very great effect can be expected in a semiconductor field. Further, since the test means can be realized by such a simple configuration where only the address data indicative of each defective portion are stored, the test means is
available at low cost.
A second embodiment will next be described with reference to FIG. 2. In the second embodiment, specific examples of configurations of the aforementioned semiconductor memory circuit 103 and decision unit 104 are illustrated. Since
configurations for every column are similar to those employed in the above embodiment, the configuration of an arbitrary column m (m=1.about.m) of a plurality of columns is shown in FIG. 2.
The semiconductor memory circuit 103 comprises a plurality of sense amplifier units SAU1 through SAUn, input/output buses I/Om for respectively reading data from the sense amplifier units (called "data read operation") or writing it into the
sense amplifier units (call "data write operation"), a data bus DB, read circuits 103Rm for respectively outputting data placed on the input/output buses I/Om to the data bus DB upon the data read operation and outputting the data placed on the
input/output buses I/Om to the decision unit 104 upon a test operation of the semiconductor memory circuit, write circuits 103Wm for writing data into their corresponding sense amplifier units through the I/O buses upon the data write operation, and
switch means SWdm (composed of N channel MOS transistors (hereinafter called "NMOSs")) each disposed between the read circuit 103Rm and the data bus DB.
The sense amplifier unit SAUn (n=1.about.n, n>m) consists of bit line pairs BLnm for respectively transferring data stored in memory cells, sense amplifiers SAnm for respectively amplifying data lying on the bit line pairs BLnm, and switch
means SWnm disposed between the sense amplifiers SAnm and the I/O buses. Each switch means SWnm is controlled by a sense amplifier unit select signal .phi. sn. Each sense amplifier SAnm is controlled by a column signal .phi. CLm supplied to a column
line CLm. In this case, when the column signal .phi. CLm is high in level, the sense amplifier SAnm is activated so as to perform an amplifying operation. This column signal is also supplied to the switch means SWdm through an inverter 103Im. In the
present embodiment, the I/O bus is disposed so as to extend in the same direction as that of the column line.
The decision unit 104 is composed of a plurality of decision circuits 104m (m=1.about.m) (each decision circuit consists of an exclusive-OR circuit in this case). Each decision circuit 104m compares an output produced from the read circuit 103Rm
with an expected value .phi. 104 outputted from the test pattern generator 102 and outputs the result of comparison therefrom.
The column signal .phi. CL and the sense amplifier unit select signal .phi. sn are generated based on decode signals supplied from unillustrated Y and X decoders or their corresponding decoders.
The operation of the configuration for the semiconductor memory circuit will next be described. However, since the read and write operations can be easily understood if the above-described conf | | |
