An all-pixel reading image sensor or a noninterlaced output image sensor, in which an interlaced signal can selectively be output without the use of a frame memory or the like as an external circuit. For outputting an interlaced signal from a three-layer three-phase drive all-pixel reading CCD image sensor, vertical shift registers are supplied with first through third vertical transfer pulses to transfer signal charges in the pixels of an nth line, for example, to a horizontal shift register, and then the horizontal shift register is supplied with horizontal transfer pulses to transfer (shift) the signal charges of the nth line stored in the horizontal shift register by two pixels, for example, to an output unit. Thereafter, the vertical shift registers are supplied with first through third vertical transfer pulses to transfer signal charges in the pixels of an (n+1)th line to the horizontal shift register, in which the signal charges of the nth line and the signal charges of the (n+1)th line are mixed with each other.
RELATED APPLICATION DATA
This is a continuation of International Application No. PCT/JP96/03609 filed Dec. 11, 1996, claiming priority to Japanese application No. P07-333644 filed Dec. 21, 1995. This Japanese application is incorporated herein by reference to the extent not already presented herein.
A solid-state imaging device including a plurality of light receiving sections; a pixel area vertical transfer register section for transferring, column by column, charges generated by the plurality of light receiving sections; a dummy area vertical transfer register section for transferring, column by column in the vertical direction, the charges which have been transferred by the pixel area vertical transfer register section, the dummy area vertical transfer register section providing a control such that the transfer of the charges of at least one of the plurality of columns is performed in the same manner as the charges in the other columns in one case, and in a different manner from the transfer of the charges in the other columns in another case; and a horizontal transfer register section for transferring, in a horizontal direction, the charges which have been transferred from the dummy area vertical transfer register section.
Systems and methods allow driving a solid-state image pickup apparatus at high-speed operation by reducing a number of different samples in the horizontal and vertical directions. In an exemplary embodiment, three or more odd-numbered pixels are incorporated into a single block and signal charges from same color outputs are added within transfer registers such that an average center of the pixels coincides with a pixel at a center of the block. Three transfer electrodes are preferably provided for a column of a vertical transfer register in a part of the vertical transfer register on a side of the horizontal transfer register. The three transfer electrodes may be formed from one layer of three different gate electrode layers. The vertical registers may be arranged in a three column cycle. Preferably, an imaging device employing this structure has a switching mode of operation between a mode in which mixed charges that result from adding signal charges of predetermined pixels from one block are output and a normal mode for outputting all pixel information.
An image-capturing element comprises: a plurality of pixels provided in a matrix each of which has a photoelectric conversion element; a plurality of color filters each of which is provided at one of the plurality of pixels; and a read out circuit that adds together electrical charges of pixels within every specific range among the plurality of pixels and enables a sequential read out of added electrical charges.
A solid state image pickup device having: a vertical addition unit for adding electric charges of two or more photoelectric conversion elements on a vertical charge transfer path, by controlling read gates and the vertical charge transfer path to read electric charges from some of the plurality of photoelectric conversion elements to the vertical charge transfer path, transfer the read electric charges on the vertical charge transfer path to the downstream side in the vertical direction, and read electric charges from others of the plurality of photoelectric elements on the downstream side to the vertical charge transfer path; and a horizontal addition unit for adding electric charges transferred from two or more of the vertical charge transfer paths, on the horizontal charge transfer path, by controlling transfer gates and the horizontal charge transfer path to transfer electric charges from some of the plurality of vertical charge transfer paths to the horizontal charge transfer path, transfer the electric charges on the horizontal charge transfer path to the downstream side in the horizontal direction, and transfer electric charges from others of the plurality of vertical charge transfer paths on the downstream side to the horizontal charge transfer path.
In a digital camera by the use of a CCD of a honeycomb array, the center positions of mixed pixels of colors B and G are fixed in (4k+1)th and (4k+2)th rows, wherein k represents an integer 0 or more, while the center positions of mixed pixels (mixed pixels R11 and R15) of a color R in the (4k+1)th row are required to be shifted to positions indicated by circles drawn by dotted lines in FIG. 4, as indicated by arrows in FIG. 4. For example, pixel values of the mixed pixels R11 and R15 are weighed in a weighing ratio of 1:3 so as to take a weighted average (i.e., (R11+3R15)/4) in such a manner that the center position of the mixed pixel R15 is shifted to a position obtained by dividing the distance between the center positions of the mixed pixels R11 and R15 at 3:1.
