Probeless testing of pad buffers on wafer

I claim:

1. A semiconductor body having at least one integrated circuit formed at a surface thereof, the at least one integrated circuit comprising:

core functional logic;

a terminal buffer coupled in a signal path between the core functional logic and a terminal pad, for forwarding a signal along the signal path;

a load test switch for selectively connecting a load terminal to the signal path between the terminal buffer and the terminal pad and free of the terminal pad;

a first test switch for selectively connecting an input of the terminal buffer to a first test terminal;

a second test switch for selectively connecting an output of the terminal buffer to a second test terminal; and

control circuitry for controlling the operation of the load test switch and the first and second test switches so as to be open in normal operation, and so as to be selectively closed in a test mode.

2. The semiconductor body of claim 1, wherein the at least one integrated circuit further comprises:

an electrostatic discharge protection circuit, connected in the signal path between the terminal pad and the terminal buffer, at a location in the signal path between the load test switch and the terminal buffer.

3. The semiconductor body of claim 1, further comprising:

a bus holder circuit connected to the terminal pad at a node that is between the terminal pad and the terminal buffer.

4. The semiconductor body of claim 1, wherein the terminal buffer comprises an output buffer, the output buffer having an input coupled to the core functional logic and having an output coupled to the terminal pad

and further comprising:

an isolation test switch, for selectively connecting the terminal buffer to the core functional logic;

wherein the control circuitry is also for controlling the operation of the isolation test switch so as to be closed in normal operation, and so as to lo be open in the test mode.

5. The semiconductor body of claim 4, further comprising:

an input buffer, having an input coupled to the terminal pad and having an output coupled to the core functional logic;

a third test switch for selectively connecting the output of the input buffer to the first test terminal;

wherein the control circuitry is also for controlling the operation of the third test switch so as to be open in normal operation, and so as to be selectively closed in the test mode.

6. The semiconductor body of claim 1, wherein a plurality of integrated circuits are formed at a surface thereof;

wherein the load terminals of the plurality of integrated circuits are connected in common;

wherein the first test terminals of the plurality of integrated circuits are connected in common;

and wherein the second test terminals of the plurality of integrated circuits are connected in common.

7. The semiconductor body of claim 1, wherein the at least one integrated circuit comprises a plurality of terminal buffers, each associated with first and second test switches and load test switches, the first test switches associated with the plurality of terminal buffers connected to a common first test node, the second test switches associated with the plurality of terminal buffers connected to a common second test node, and the load test switches associated with the plurality of terminal buffers connected to a common load node;

and further comprising:

first, second, and third pad switches, connected in series between the first common test node and the first test terminal, the second common test node and the second test terminal, and the common load node and the load terminal, respectively;

wherein the control circuitry is also for controlling the operation of the first, second, and third pad switches so as to be open in normal operation and so as to be selectively closed in the test mode.

8. The semiconductor body of claim 1, further comprising:

an input buffer, having an input coupled to the terminal pad and having an output coupled to the core functional logic;

said first switch for selectively connecting the output of the input buffer to the first test terminal.

9. A method of testing output circuitry of an integrated circuit, the output circuitry including an output buffer having an input coupled to core functional circuitry and an output coupled to a terminal pad, comprising the steps of:

disconnecting the input of the output buffer from the core functional circuitry;

connecting the input of the output buffer to a first test terminal;

connecting the output of the output buffer to a second test terminal;

applying a test input signal at a first logic level to the first test terminal, for receipt by the input of the output buffer;

measuring, at the second test terminal, the drive strength of the output buffer in response to the test input signal at the first logic level;

applying a test input signal at a second logic level to the first test terminal, for receipt by the input of the output buffer; and

measuring, at the second test terminal, the drive strength of the output buffer in response to the test input signal at the second logic level.

10. The method of claim 9, wherein the method further comprises:

connecting the output of the output buffer to a load test terminal;

connecting a load to the load test terminal prior to the applying steps;

and wherein the measuring steps each comprise:

measuring a voltage drop across the load to determine a drive current from the output buffer.

11. The method of claim 9, wherein the method further comprises:

connecting the output of the output buffer to the load test terminal;

disabling the output buffer;

applying a varying test voltage to the load test terminal;

measuring the voltage at the second test terminal to determine if the voltage at the output of the output buffer follows the varying test voltage.

12. The method of claim 9, wherein the output buffer has a drive input for receiving a drive signal controlling the drive level of the output buffer;

wherein the integrated circuit further comprises a boundary scan cell connected between the drive input of the output buffer and the core functional logic, for providing the drive signal to the output buffer;

and wherein the method further comprises:

storing a selected drive signal in the boundary scan cell, prior to the applying steps.

13. The method of claim 9, wherein the integrated circuit includes a plurality of output buffers, each associated with one of a plurality of terminal pads, and each of the output buffers also associated with a plurality of control switches, the plurality of control switches comprising, for each of the output buffers, an isolation control switch connected between the core functional circuitry and the input of the output buffer, a first test switch connected between the input of the output buffer and the first test terminal, and a second test switch connected between the output of the output buffer and the second test terminal;

wherein the integrated circuit further comprises a first test pad control switch connected between the first test terminal and each of the first test switches of the plurality of output buffers, and a second test pad control switch connected between the second test terminal and each of the second test switches of the plurality of output buffers;

and wherein the method further comprises:

prior to the applying step, closing the first and second test pad control switches.

14. The method of claim 9, wherein each measuring step measures a propagation delay between the applying step and a time at which the output buffer drives the second test terminal to a threshold voltage.

15. The method of claim 9, wherein the integrated circuit is disposed on a semiconductor wafer in combination with a plurality of similar integrated circuits;

wherein each of the plurality of integrated circuits includes output circuitry including an output buffer having an input coupled to core functional circuitry and an output coupled to a terminal pad;

and wherein each of the plurality of integrated circuits includes a plurality of control switches, the plurality of control switches comprising an isolation control switch connected between the core functional circuitry and the input of the output buffer, a first test switch connected between the input of the output buffer and the first test terminal, and a second test switch connected between the output of the output buffer and the second test terminal, the first and second test terminals of each of the plurality of integrated circuits being connected together to first and second test bus conductors.

16. An integrated circuit, comprising:

functional circuitry having at least one output;

an output buffer having an input, and having an output coupled to an externally accessible functional terminal of the integrated circuit; and

a first switch for selectably coupling the input of the output buffer to an output of the functional circuitry;

a second switch for selectably coupling the input of the output buffer to an externally accessible test terminal on the integrated circuit; and

control circuitry for closing the first switch and opening the second switch, during functional operation of the integrated circuit.

17. The integrated circuit of claim 16, wherein the control circuitry is also for opening the first switch and closing the second switch, during test operation of the integrated circuit.

18. A method of testing an output buffer on an integrated circuit, comprising the steps of:

isolating an input of the output buffer from functional circuitry on said integrated circuit;

connecting the input of the output buffer to an externally accessible terminal of the integrated circuit;

after the connecting step, applying test signals to the externally accessible terminal of the integrated circuit; and

comparing output signals generated by the output buffer responsive to the applying step to expected signals corresponding to the test signals.

19. A semiconductor body upon which at least one integrated circuit is disposed, said at least one integrated circuit comprising:

functional circuitry having at least one output;

an output buffer having an input, and having an output coupled to an externally accessible functional terminal of the integrated circuit; and

a first switch for selectably coupling the input of the output buffer to an output of the functional circuitry;

a second switch for selectably coupling the input of the output buffer to an externally accessible test terminal on the integrated circuit; and

control circuitry for closing the first switch and opening the second switch, during functional operation of the integrated circuit.

20. The semiconductor body of claim 19, wherein the control circuitry is also for opening the first switch and closing the second switch, during test operation of the integrated circuit.

21. The semiconductor body of claim 19, wherein a plurality of integrated circuits are disposed thereupon;

and wherein each of the plurality of integrated circuits comprises:

functional circuitry having at least one output;

an output buffer having an input, and having an output coupled to an externally accessible functional terminal of the integrated circuit; and

a first switch for selectably coupling the input of the output buffer to an output of the functional circuitry;

a second switch for selectably coupling the input of the output buffer to an externally accessible test terminal on the integrated circuit; and

control circuitry for closing the first switch and opening the second switch, during functional operation of the integrated circuit.

22. The semiconductor body of claim 21, wherein the control circuitry of each of the plurality of integrated circuits is also for opening the first switch and closing the second switch, during test operation of the integrated circuit.

23. The semiconductor body of claim 22, wherein a plurality of integrated circuits are disposed thereupon.

24. A semiconductor body upon which at least one integrated circuit is disposed, said at least one integrated circuit comprising:

functional circuitry having an output;

an output buffer, having an input, and having an output coupled to an externally accessible functional terminal of the integrated circuit;

a first switch for selectably coupling the input of the output buffer to an output of the functional circuitry;

a second switch for selectably coupling the input of the output buffer to a first externally accessible test terminal on the integrated circuit;

a third switch for selectably coupling the output of the output buffer to a second externally accessible test terminal on the integrated circuit; and

control circuitry for closing the first switch and opening the second and third switches, during functional operation of the integrated circuit.

25. The semiconductor body of claim 24, wherein the control circuitry is also for opening the first switch and closing the second and third switches, during test operation of the integrated circuit.

26. A method of testing an input buffer on an integrated circuit, the input buffer having an input coupled to an external functional terminal, the method comprising the steps of:

applying a varying voltage to a first external test terminal also coupled to the input of the input buffer; and

monitoring an output of the input buffer at a second external test terminal coupled to the output of the input buffer during the applying of the varying voltage, to detect changes in voltage at the output of the input buffer.

27. A method of testing input circuitry of an integrated circuit, the input circuitry including an input buffer having an input coupled to a terminal pad and an output coupled to core functional circuitry, comprising the steps of:

connecting the input of the input buffer to a first test terminal;

connecting the output of the input buffer to a second test terminal;

applying a test input signal at a first logic level to the first test terminal, for receipt by the input of the input buffer;

measuring, at the second test terminal, the response of the input buffer to the applying step.

28. The method of claim 27, wherein the applying step comprises:

varying the voltage applied to the first test terminal within an input low level voltage range;

and wherein the measuring step comprises:

monitoring a logic level at the second test terminal to determine whether the logic level remains constant during the varying step;

and further comprising:

varying the voltage applied to the first test terminal within an input high level voltage range; and

monitoring a logic level at the second test terminal to determine whether the logic level remains constant during the step of varying the applied voltage within the input high level voltage range.

29. The method of claim 27, wherein the applying step comprises:

varying the voltage applied to the first test terminal from within a first voltage range to at or beyond a first threshold voltage outside of the first voltage range;

wherein the measuring step comprises:

monitoring a logic level at the second test terminal to determine whether the logic level changed state responsive to the varying step;

and wherein the method further comprises:

responsive to the monitoring step determining that the logic level changed state, again varying the voltage applied to the first test terminal from at or beyond the first threshold voltage to a second threshold voltage nearer to the first voltage range than the first threshold voltage; and

again monitoring a logic level at the second test terminal to determine whether the logic level changed state responsive to the step of varying the voltage applied to the first test terminal from at or beyond the first threshold voltage to the second threshold voltage.

30. The method of claim 27, wherein the integrated circuit is disposed on a semiconductor wafer in combination with a plurality of similar integrated circuits;

wherein each of the plurality of integrated circuits includes input circuitry including an input buffer having an input coupled to a terminal pad and an output coupled to core functional circuitry;

wherein each of the plurality of integrated circuits includes a plurality of control switches, the plurality of control switches comprising a first test switch connected between the input of the input buffer and the first test terminal, and a second test switch connected between the output of the input buffer and the second test terminal, the first and second test terminals of each of the plurality of integrated circuits being connected together to first and second test bus conductors.

31. A method of testing for the absence of output drive capability at an input of a first circuit, the output being connected to an output bond pad, comprising

a. disabling the output of the first circuit;

b. connecting an output of a second circuit to the output of the first circuit between the output of the first circuit and the bond pad and free of the bond pad;

c. outputting a varying voltage from the output of the second circuit; and

d. during the outputting step, monitoring current flow in the connection between the outputs of the first and second circuits.

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

The present invention relates generally to testing an integrated circuit die on a wafer without physically probing its bond pads and, more particularly, to testing the pad buffers, electrostatic discharge protection circuitry, and pad bus holders of the die without physically probing the bond pads.

Scan testing of circuits is well known. Scan testing configures the circuit into scan cells and combinational logic. Once so configured, the scan cells are controlled to capture test response data from the combinational logic, then shifted to unload the captured test response data from the combinational logic and to load the next test stimulus data to apply to the combinational logic.

FIG. 1 shows an electrical circuit having three memories (M) A,B,C and combinational logic (CL). FIG. 2 shows an example of the memories of FIG. 1 implemented as D flip flops (FF), each memory having a data input, data output, and clock and reset control signals. FIG. 3 shows one example of how the circuit of FIG. 1 can be made scan testable by converting the memories into scan cells and connecting the outputs (D,E,F) of the combinational logic to the scan cell capture inputs. FIG. 4A shows an example of how a D flip flop based memory is converted into a scan cell. The scan cells have a 3:1 multiplexer input to the flip flop. The multiplexer receives selection control (S) to: (1) input the output of the combinational logic to the flip flop (Input1, the capture input), (2) input the external input to the flip flop (Input2, the functional input), or (3) input the serial input to the flip flop (SI, the shift input). The flip flop receives a clock (C) and a reset (R) control input. The scan cells are connected together via their serial input (SI) and serial output (SO) to form a 3-bit scan path through the circuit of FIG. 3. The three scan cells operate as the state memories during functional operation. During test operation, the scan cells operate as scan cells to allow inputting test stimulus to the combinational logic and capturing the response output from the combinational logic. While edge sensitive D flip flop memories are used in this disclosure, level sensitive memories could be used as well. Converting level sensitive memories into scan memories is well known.

In the FIG. 3 example, the scan cells perform both the input of stimulus to the combinational logic and the capture of response from the combinational logic. In other examples of how the circuit may be made scan testable, scan cells could be added to the circuit and scan path, and coupled to the outputs of the combinational logic, as shown in the dotted boxes in FIG. 3. This would allow the input stimulus to be supplied by the converted scan cells (A,B,C) and the output response captured by the added scan cells. Adding scan cells for the purpose of capturing response data adds circuitry. Also if scan cells are added to capture the combinational logic response, the converted scan cells A,B,C do not need Input1 and the feedback connections from the combinational logic outputs.

Also in FIG. 3 a bypass memory (BM) is shown to allow a single bit bypass scan path through the circuit from SI to SO. The use of scan bypass memories is well known. An example of the bypass memory is shown in FIG. 4B. In addition to providing conventional bypassing of the circuit, the bypass memory of the present invention is required to maintain its present state during capture operations, and to always load data from SI regardless of whether it is selected between SI and SO or not. The multiplexer of the bypass memory and the selection (S) control it receives allow these two requirements to be met.

FIG. 5 shows three of the circuits of FIG. 3 connected in series to a tester. The tester outputs data to the serial input of the first circuit (C1) and receives data from the serial output of the last circuit (C3). The tester outputs control to all three circuits to regulate their scan cell's capture and shift operations during each scan test cycle.

FIG. 6 shows the concept of conventional scan testing. In FIG. 6, N circuits are connected on a scan path. A tester controls all circuits C1-N to reset. Following reset, the tester controls all circuits C1-N to capture the first response data to the reset stimulus data. Next the tester controls all circuits C1-N to shift out the first captured response data and shift in the second stimulus data. This process of capturing response data, shifting out the response data while new stimulus data is shifted in is repeated for the number of patterns (P) required to test each of the circuits 1-N. As the number of serially connected circuits (N) grows, so does the length (L) of the scan path the tester needs to traverse during each capture/shift cycle. The test time in clocks, using conventional scan testing, is equal to the sum of the scan path lengths (L) of each circuit (N) in the scan path times the number of patterns (P) to be applied.

Example 1 shows how three circuits (C1, C2, and C3) are conventionally scan tested by a tester as shown in FIG. 5. The combinational logic decode for each of the circuits C1, C2, and C3 are shown in the Tables of Example 1. The tables show the present state (PS) output (i.e. stimulus) of the scan cells (ABC) to the combinational logic and the next state (NS) input (i.e. response) to the scan cells (ABC) from the combinational logic. At the beginning of the test, the tester outputs control to reset all scan cells to a first present state (PS1). Next, the tester outputs control to all scan cells to do a first capture (CP1) of the response output of the combinational logic (CL) to the PS1 stimulus. Next, the tester outputs control to do a first 9-bit shift operation (SH1) to unload the first captured response data from each circuit's scan cells and to load the second present state (PS2) stimulus data to each circuit's scan cells. Next, the tester does a second capture (CP2) to load the scan cells with the response data from the second present state (PS2) stimulus data, then does a second 9-bit shift (SH2) to unload the second captured response data and load the third stimulus data. Next, the tester does a third capture (CP3) to load the scan cells with the response data from the third present state (PS3) stimulus data, then does a third 9-bit shift (SH3) to unload the third captured response data and load the fourth stimulus data (11). This process continues through an eighth capture (CP8) to load the scan cells with the response data from the eighth present state (PS8) stimulus data, then does an eighth 9-bit shift (SH8) to unload the final captured response data. The data input to the scan cells during the eighth shift (SH8) can be don't care data (x) since testing is complete following the eighth shift. If all circuits are good the response shifted out for each PS1-8 stimulus will match the expected response as shown in the tables for C1, C2, and C3. The number of test clocks for the conventional scan testing of the circuits in example 1 is the sum of the capture clocks (CP1-8) and shift clocks (SH1-8), or 8+(8.times.9)=80.

It is desirable to scan test electrical circuits in less time than the conventional approach.

The present invention accelerates scan testing by re-using one circuit's scan test response data as scan test stimulus data for another circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a known electrical circuit having three memories.

FIG. 2 is a block diagram of one memory part of FIG. 1.

FIG. 3 is a block diagram of a circuit having a 3-bit scan path.

FIGS. 4A and 4B are block diagrams of a bypass memory of FIG. 3,

FIG. 5 is a block diagram of three circuits of FIG. 3 connected in series to a tester.

FIG. 6 is a block diagram of N circuits connected on a scan path in a known manner.

FIG. 7 is a block diagram of N circuits connected on a scan path according to the disclosed invention.

FIG. 8 is a block diagram of N circuits connected on a scan path and depicting N progressive scan test patterns.

FIG. 9 is a block diagram of a circuit similar to that in FIG. 3 with only a 2-bit scan path.

FIG. 10 is a block diagram of a circuit similar to that in FIG. 3 with a greater number of outputs than inputs.

FIG. 11 is a block diagram of a scan cell C of FIG. 10.

FIG. 12 is a block diagram of the circuit of FIG. 10 modified to accept the warping scan test concept.

FIG. 13 is a block diagram of a summing cell (DSC).

FIG. 14 is a block diagram of a scan testable circuit.

FIG. 15 is a block diagram of a data retaining cell (DRC).

FIG. 16 is a block diagram of an implementation of a warping scan test concept.

FIG. 17 is a block diagram of another implementation of a warping scan test concept.

FIG. 18 is a block diagram of another implementation of a warping scan test concept.

FIG. 19 is a block diagram of a data capture boundary cell (DCBC).

FIG. 20 is a block diagram of a data retaining boundary cell (DRBC).

FIG. 21 is a block diagram of a data summing boundary cell (DSBC).

FIG. 21A is a block diagram of a realization of DCBC, DRBC, and DSBC.

FIG. 22 is a block diagram of circuits C1-CN being tested inside an IC or die.

FIG. 23 is a block diagram of ICs 1-N being tested on a circuit board.

FIG. 24 is a block diagram of boards BD being tested in a box.

FIG. 25 is a block diagram of multiple boxes 1-N being tested in a system.

FIG. 26 is a representation of dies being tested on a wafer.

FIG. 27 is a block diagram of a test access port on a die.

FIG. 26 is a representation of wafers, each carrying dies, being tested in a lot.

FIG. 29 is a representation of wafer lots 1-N being tested.

FIG. 30 is a block diagram of a circuit and scan path with conventional signature analyzers.

FIG. 31 is a representation of a wafer with additional bussing and test pads.

FIG. 32 is a block diagram of a test access port on a die.

FIG. 33 is a block diagram of a conventional IEEE STD 1149.1 scan cell.

FIG. 34 is a block diagram of a circuit using four conventional scan cells S.

FIG. 35 is a block diagram of a circuit similar to that of FIG. 34.

FIG. 36 is a block diagram of a circuit relating to an input buffer.

FIG. 37 is a block diagram of a circuit relating to a bi-directional pad.

FIG. 38 is a block diagram of the circuits of FIGS. 34-37 bussed together on a die.

FIG. 39A is a block diagram of a 3-state output buffer.

FIG. 39B is a block diagram of a known ESD circuit.

FIG. 39C is a block diagram of another known ESD circuit.

FIG. 40A is a block diagram of a tester and an input buffer.

FIG. 40B is a block diagram of a known ESO circuit.

FIG. 41 is a block diagram of a tester and an analog output buffer.

FIG. 42 is a block diagram of a tester and an analog input buffer.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 7 shows the warping scan test concept of the present invention. The term warping is used to indicate the non-conventional way serial data propagates through circuits during scan testing according to the present invention. In FIG. 7, N circuits are connected on a scan path. A tester controls all circuits C1-N to reset. Following reset, the tester controls all circuits C1-N to capture the first response data to the reset stimulus data. Next the tester controls all circuits C1-N to shift data, but only for the length of the first circuit's (C1) scan path. After the first shift operation, C1's scan path is loaded with stimulus data from the tester and C2-CN's scan path is loaded with the response data from C1-CN-1. During the next capture and shift operation, C1 outputs response data to downstream circuits and receives its next stimulus data from the tester. After the second capture and shift operation, C 1 contains its second stimulus data pattern from the tester and C2-CN contain their second stimulus patterns derived from the response output from leading circuits C1--CN--1. This process continues until C1 is tested. After C1 is tested, it is bypassed so that the tester can directly input any remaining stimulus to C2 and allow response from C2 to ripple downstream as stimulus to trailing circuits C3-CN. Similarly, after C2 is tested, it is bypassed to allow direct input of remaining stimulus to C3 while response from C3 is rippled downstream as stimulus to trailing circuits C4-CN. The overall testing of circuits C1-CN in FIG. 7 is complete when all circuits have received their required input stimulus, either indirectly as a result of output response from leading circuits or by direct input from the tester, and have output their response to the tester.

FIG. 8 shows a conceptual flow of the above described warping scan test operation as it progresses across circuits C1-CN. The test sessions of FIG. 8 indicate times when a tester is inputting stimulus to a given circuit scan path, either directly to C1 or through tested and bypassed circuits (C1--CN--1). The shaded area in each circuit C1-CN indicates reduction of remaining stimulus input to a circuit following a given test session. When a circuit is completely tested, it is shown to be bypassed and completely shaded. The progression of the shaded areas of each circuit indicate the test acceleration anticipated by the present invention. For example, following test session 1 (C1 tested), the response generated to downstream circuits C2-CN during test session 1 has reduced their need for additional stimulus patterns from the tester by 50%. Following test session 2 (C2 tested), the response generated to downstream circuits C3-CN during test session 2 has reduced their need for additional stimulus patterns from the tester by another 50%. And so on. The present invention will show that scan test time can be dramatically reduced by using output response from leading circuits as stimulus input to trailing circuits which can reduce or even eliminate the need of stimulus input from the tester.

Example 2 shows how the same three circuits (C1,C2,C3) of Example 1 would be tested using the warping scan test concept whereby response data from leading circuits is used as stimulus data in trailing circuits. At the beginning of the test, the tester outputs control to reset or initialize all scan cells to a first present state 1 (PS1). Note that while a reset input is provided on the scan cells to allow the tester to initialize the scan paths by a reset control signal (as seen in FIG. 4A), the tester could also initialize non-resetable scan cells by doing a scan operation. Next, the tester outputs control to all scan cells to do a first capture (CP1) of the response output of the combinational logic (CL) to the first present state (PS1) stimulus. The tester then outputs control to cause all scan cells of circuits C1 through C3 to do a first 3-bit shift operation (SH1). The first 3-bit shift operation unloads the first captured 3-bit response data from C3, moves the first captured 3-bit response data from C1 to C2 and from C2 to C3, and loads the second 3-bit stimulus data into C1.

Next, the tester outputs control to all scan cells to do a second capture (CP2) of the response output of the combinational logic (CL) to the PS2 stimulus. The tester then outputs control to cause all scan cells of circuits C1 through C3 to do a second 3-bit shift operation (SH2). The second 3-bit shift operation unloads the second captured 3-bit response data from C3, moves the second captured 3-bit response data from C1 to C2 and from C2 to C3, and loads the third 3-bit stimulus data into C1.

Next, the tester outputs control to all scan cells to do a third capture (CP3) of the response output of the combinational logic (CL) to the PS3 stimulus. The tester then outputs control to cause all scan cells of circuits C1 through C3 to do a third 3-bit shift operation (SH3). The third 3-bit shift operation unloads the third captured 3-bit response data from C3, moves the third captured 3-bit response data from C1 to C2 and from C2 to C3, and loads the fourth 3-bit stimulus data into C1.

This capture and shift process repeats until the seventh shift operation (SH7). During SH7, the tester unloads the seventh captured 3-bit response from C3, moves the seventh captured 3-bit response data from C1 to C2 and from C2 to C3, and loads the eighth, and last, 3-bit stimulus data into C1.

Next, the tester outputs control to all scan cells to do an eighth capture (CP8) of the response output of the combinational logic (CL) to the PS8 stimulus. The tester then outputs control to cause all scan cells of circuits C1 through C3 to do an eighth 3-bit shift operation (SH8). The eighth 3-bit shift operation unloads the eighth captured 3-bit response data from C3, moves the eighth captured 3-bit response data from C1 to C2 and from C2 to C3, and inputs the first bit of the first 3-bit C2 stimulus pattern into C1's bypass memory (BM). Note that the serial input during SH8 is 1xx because the leading two bits (xx) will not be used, while the last bit (1) will be stored in C1's bypass memory and be the first bit of the first 3-bit stimulus pattern input to C2 during SH9. As previously mentioned in regard to FIG. 3, the bypass memory always loads the data from SI during shift operations and maintains its data during capture operations. This allows the present invention to use bypass memories as data pipeline bits between the tester and circuit receiving stimulus input from the tester.

Following SH8, C