First and second bus bridges, e.g., first and second RAID disk controllers, are operative to communicate between a first bus and a second bus via respective first and second caches and to transfer information from the first bus bridge to the second cache over a third bus, e.g., a synchronous data link between the caches, to allow recovery of data previously cached in the first cache via the second bus bridge. The second bus bridge preferably is operative to transfer information addressed to the first bus from the first bus to the second bus, e.g., to "alias" addresses normally assigned to the first bus bridge in event of a failure, disconnection or other change in status of the first bus bridge. The status may be communicated from the first bus bridge to the second bus bridge over a fourth bus connecting the first and second bus bridges. In one embodiment, the first and second bus bridges are included in respective first and second circuit assemblies that are connected to the first and second busses and to one another by a conductor assembly, e.g., a relatively high-reliability passive backplane. In yet another embodiment according to the present invention, a a respective one of the first and second circuit assemblies comprises a first circuit substrate configured to be releasably connected to the conductor assembly. The first circuit substrate is configured to receive a plurality of second circuit substrates for connecting the bus bridge of the circuit assembly to the first and second busses. In this manner, the circuit assemblies may be adapted to bridge a variety of bus types, such as low-voltage differential SCSI (LVDS), single-ended ended SCSI (SCSI-SE) and Fibre Channel (FC).
A method for monitoring the availability of a data processing system is proposed. For example, the system runs a management application, which involves the periodic transmission of blocks of data from multiple local computers to a central computer. In the method of the invention, whenever a block of data must be transmitted by a generic local computer, an expected transmission delay of a next block of data is estimated; this information is then attached to the block of data. As a result, the central computer receiving the updated block of data can calculate an expected receiving time of the next block of data accordingly. If the next block of data is not received in due time, the central computer determines a failure of the local computer. Preferably, the central computer also scans a subset of ports of the local computer, so as to ascertain whether the problem is due to a temporary unavailability of the application or to an actual crash of the local computer.
A method and apparatus for cache coherency in storage system is disclosed. The invention maintains cache coherency in the controller system of the storage system in a manner to minimize the performance degradation to a host system, and to allow the caches to be coherent without requiring data to be written to the backing disks. Each controller manages an area of memory on the partner controller, but the area is managed dynamically and is done with the information about the partner controller. A first controller determines which mirror cache line on a second controller to copy data into, and then mirrors the data from a first controller cache line to a second controller cache line. A message is sent from the first controller to the second controller informing the second controller of cache meta data associated with the mirror cache line so that the cache line may be added to the second controller's hash table.
The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply voltage to periphery circuitry and an array voltage bus may supply voltage to array circuitry. A bridge circuit may be utilized to isolate the buses from each other and couple the buses together, depending on the control signals are received by the bridge circuit. As such, the bridge circuit enhances the operation of the memory device by reducing duplicative circuits and equalizing the voltage that are applied to the buses. In addition, the bridge circuit isolates the buses from each other to protect sensitive circuitry in the array and periphery circuitry from noise on the other bus.
The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply voltage to periphery circuitry and an array voltage bus may supply voltage to array circuitry. A bridge circuit may be utilized to isolate the buses from each other and couple the buses together, depending on the control signals are received by the bridge circuit. As such, the bridge circuit enhances the operation of the memory device by reducing duplicative circuits and equalizing the voltage that are applied to the buses. In addition, the bridge circuit isolates the buses from each other to protect sensitive circuitry in the array and periphery circuitry from noise on the other bus.
One embodiment of a system for disabling a computer bus upon detection of a power fault includes a bus bridge device coupled to a bus and a power regulator that delivers power to the bus. If the power regulator detects a power fault, then the power regulator asserts a fault signal to the bus bridge device. The power regulator also removes power from the bus. The bus bridge device disconnects an internal logic unit from the bus in response to the assertion of the fault signal. The bus bridge device, in further response to the assertion of the fault signal, alerts the system of the power fault by asserting an interrupt signal.
