Circuit and method for refreshing data stored in a memory cell

Claims

What is claimed:

1. An integrated circuit, comprising:

a memory array having memory cells for storing data, the memory array operable to fully or substantially fully refresh the data stored in a memory cell during a respective refresh cycle of a refresh mode; and

a refresh circuit coupled to the memory array, the refresh circuit operable during a first portion of the refresh mode to implement a first series of refresh cycles in the memory array at a first frequency, the refresh circuit operable during a second portion of the refresh mode to implement a second series of refresh cycles in the memory array at a second frequency.

2. The integrated circuit of claim 1 wherein:

the data stored in the memory cells has respective signal levels; and

the memory array includes a sense amplifier that is operable to refresh the data stored in a memory cell during a respective refresh cycle by amplifying the signal level of the data and coupling the amplified signal level to the memory cell.

3. An integrated circuit, comprising:

a memory array having memory cells for storing data, the memory array operable to refresh the data stored in a memory cell during a respective refresh cycle of a refresh mode;

a refresh circuit coupled to the memory array, the refresh circuit operable during a first portion of the refresh mode to implement a first series of refresh cycles in the memory array at a first frequency, the refresh circuit operable during a second portion of the refresh mode to implement a second series of refresh cycles in the memory array at a second frequency;

wherein the data stored in each of the memory cells has a respective signal level within a first range if the data equals a first logic value and has a respective signal level in a second range if the data equals a second logic value, the first range of signal levels having a maximum signal level, the second range of signal levels having a minimum signal level;

wherein the memory array includes a sense amplifier that is operable to refresh the data stored in each memory cell during a respective refresh cycle by amplifying the signal level of the data and coupling the amplified signal level to the memory cell; and

wherein the refresh circuit is operable to activate the sense amplifier for a refresh portion of each refresh cycle, the refresh portion having a duration sufficient to allow the sense amplifier to refresh the data stored in a memory cell to substantially the maximum signal level if the data equals the first logic value and to refresh the data stored in the memory cell to substantially the minimum signal level if the data equals the second logic value.

4. An integrated circuit, comprising:

a memory array having memory cells for storing data, the memory array operable to refresh the data stored in a memory cell during a respective refresh cycle of a refresh mode;

a refresh circuit coupled to the memory array, the refresh circuit operable during a first portion of the refresh mode to implement a first series of refresh cycles in the memory array at a first frequency, the refresh circuit operable during a second portion of the refresh mode to implement a second series of refresh cycles in the memory array at a second frequency;

wherein the data stored in each of the memory cells has a respective signal level within a first range if the data equals logic 1 and has a respective signal level in a second range if the data equals logic 0, the first range of signal levels having a maximum signal level, the second range of signal levels having a minimum signal level;

wherein the memory array includes a sense amplifier that is operable to refresh the data stored in each memory cell during a respective refresh cycle by amplifying the signal level of the data and coupling the amplified signal level to the memory cell; and

wherein the refresh circuit is operable to activate the sense amplifier for a refresh portion of each refresh cycle, the refresh portion having a duration sufficient to allow the sense amplifier to refresh the data stored in a memory cell to substantially the maximum signal level if the data equals logic 1 and to refresh the data stored in the memory cell to substantially the minimum signal level if the data equals logic 0.

5. An integrated circuit, comprising:

a memory array having memory cells for storing data, the memory array operable to refresh the data stored in a memory cell during a respective refresh cycle of a refresh mode;

a refresh circuit coupled to the memory array, the refresh circuit operable during a first portion of the refresh mode to implement a first series of refresh cycles in the memory array at a first frequency, the refresh circuit operable during a second portion of the refresh mode to implement a second series of refresh cycles in the memory array at a second frequency;

wherein the data stored in each of the memory cells has a respective signal level within a first range if the data equals logic 0 and has a respective signal level in a second range if the data equals logic 1, the first range of signal levels having a maximum signal level, the second range of signal levels having a minimum signal level;

wherein the memory array includes a sense amplifier that is operable to refresh the data stored in each memory cell during a respective refresh cycle by amplifying the signal level of the data and coupling the amplified signal level to the memory cell; and

wherein the refresh circuit is operable to activate the sense amplifier for a refresh portion of each refresh cycle, the refresh portion having a duration sufficient to allow the sense amplifier to refresh the data stored in a memory cell to substantially the maximum signal level if the data equals logic 0 and to refresh the data stored in the memory cell to substantially the minimum signal level if the data equals logic 1.

6. An integrated circuit, comprising:

a memory array having memory cells for storing data, the memory array operable to refresh the data stored in a memory cell during a respective refresh cycle of a refresh mode;

a refresh circuit coupled to the memory array, the refresh circuit operable during a first portion of the refresh mode to implement a first series of refresh cycles in the memory array at a first frequency, the refresh circuit operable during a second portion of the refresh mode to implement a second series of refresh cycles in the memory array at a second frequency;

wherein the memory array refreshes the respective data in each of the memory cells once during the first portion of the refresh mode; and

wherein the first frequency is significantly higher than the second frequency.

7. An integrated circuit, comprising:

a memory array having memory cells for storing data, the memory array operable to refresh the data stored in a memory cell during a respective refresh cycle of a self-refresh mode; and

a refresh circuit coupled to the memory array, the refresh circuit operable during a first portion of the self-refresh mode to implement a first series of refresh cycles in the memory array at a first frequency, the refresh circuit operable during a second portion of the self-refresh mode to implement a second series of refresh cycles in the memory array at a second frequency.

8. An integrated circuit, comprising:

a memory array having memory cells for storing data, the memory array operable to refresh the data stored in a memory cell during a respective refresh cycle; and

a refresh circuit coupled to the memory array, the refresh circuit operable during a first refresh mode to implement in the memory array a refresh cycle having a refresh portion of a first duration, the refresh circuit operable during a second refresh mode to implement in the memory array a refresh cycle having a refresh portion of a second duration that is different than the first duration.

9. The integrated circuit of claim 8 wherein:

the second duration is significantly longer than the first duration;

the first refresh mode comprises an auto-refresh mode; and

the second refresh mode comprises a self-refresh mode.

10. The integrated circuit of claim 8 wherein:

the first duration approximately equals 60 nanoseconds; and

the second duration approximately equals 80 nanoseconds.

11. The integrated circuit of claim 8 wherein:

the data stored in each of the memory cells has a respective signal level within a first range if the data equals a first logic value and has a respective signal level in a second range if the data equals a second logic value, the first range of signal levels having a maximum signal level, the second range of signal levels having a minimum signal level;

the memory array includes a sense amplifier that is operable to refresh the data stored in each memory cell during a respective refresh cycle by amplifying the signal level of the data and coupling the amplified signal level to the memory cell; and

the refresh circuit is operable to activate the sense amplifier for the first duration during the refresh portion of the first refresh cycle and for the second duration during the refresh portion of the second refresh cycle, the first duration being insufficient and the second duration being sufficient to allow the sense amplifier to refresh the data stored in a respective memory cell to substantially the maximum signal level if the data equals the first logic value and to refresh the data stored in the memory cell to substantially the minimum signal level if the data equals the second logic value.

12. An integrated circuit, comprising:

a memory array having memory cells for storing data, the memory cells arranged in one or more rows that each include a respective one or more memory cells, the memory array operable to fully or substantially fully refresh the data stored in the memory cell or cells of a row during a respective refresh cycle of a refresh mode; and

a refresh circuit coupled to the memory array, the refresh circuit operable during a first portion of the refresh mode to implement a first series of refresh cycles in the memory array at a first frequency, the refresh circuit operable during a second portion of the refresh mode to implement a second series of refresh cycles in the memory array at a second frequency that is significantly lower than the first frequency.

13. An integrated circuit, comprising:

a memory array having memory cells for storing data, the memory cells arranged in one or more rows that each include a respective one or more memory cells, the memory array operable to refresh the data stored in the memory cell or cells of a row during a respective refresh cycle of a refresh mode; and

a refresh circuit coupled to the memory array, the refresh circuit operable during a first refresh mode to implement in the memory array a refresh cycle having a refresh portion of a first duration, the refresh circuit operable during a second refresh mode to implement in the memory array a refresh cycle having a refresh portion of a second duration that is significantly longer than the first duration.

14. An integrated circuit, comprising:

a memory array having memory cells for storing data, the memory array operable to receive a refresh address and to fully or substantially fully refresh the data stored in a memory cell located at the refresh address during a respective refresh cycle of a refresh mode;

a refresh clock circuit operable to generate a refresh clock signal having a first frequency during a first portion of the refresh mode and having a second frequency during a second portion of the refresh mode, each period of the clock signal corresponding to a respective refresh cycle, the first frequency being significantly higher than the second frequency; and

a refresh address circuit coupled to the memory array and to the refresh clock circuit, the refresh address circuit operable to generate the refresh address and to update the refresh address once during each period of the refresh clock signal.

15. An integrated circuit, comprising:

a memory array having memory cells for storing data, the memory array operable to receive a refresh address and to refresh the data stored in a memory cell located at the refresh address during a respective refresh cycle of a refresh mode;

a refresh clock circuit operable to generate a refresh clock signal having a first frequency during a first portion of the refresh mode and having a second frequency during a second portion of the refresh mode, each period of the clock signal corresponding to a respective refresh cycle, the first frequency being significantly higher than the second frequency; and

a refresh address circuit coupled to the memory array and to the refresh clock circuit, the refresh address circuit operable to generate the refresh address and to update the refresh address once during each period of the refresh clock signal by incrementing the refresh address by 1.

16. An integrated circuit, comprising:

a memory array having memory cells for storing data, the memory array operable to receive a refresh address and to refresh the data stored in a memory cell located at the refresh address during a respective refresh cycle of a refresh mode;

a refresh clock circuit operable to generate a refresh clock signal having a first frequency during a first portion of the refresh mode and having a second frequency during a second portion of the refresh mode, each period of the clock signal corresponding to a respective refresh cycle, the first frequency being significantly higher than the second frequency;

a refresh address circuit coupled to the memory array and to the refresh clock circuit, the refresh address circuit operable to generate the refresh address and to update the refresh address once during each period of the refresh clock signal;

wherein the data stored in each of the memory cells has a respective signal level within a first range if the data equals a first logic value and has a respective signal level in a second range if the data equals a second logic value, the first and second ranges of signal levels having respective first and second full signal levels;

wherein the memory array includes a sense amplifier that is operable to refresh the data stored in a memory cell during a respective refresh cycle by amplifying the signal level of the data and coupling the amplified signal level to the memory cell; and

a sense-amplifier control circuit coupled to the memory array and to the refresh clock circuit, the sense-amplifier circuit operable to activate the sense amplifier during a respective refresh portion of each refresh cycle, the refresh portion having a duration that causes the sense amplifier to refresh the data stored in a respective memory cell to substantially the first full signal level if the data equals the first logic value and to substantially the second full signal level if the data equals the second logic value.

17. An integrated circuit, comprising:

a memory array having memory cells for storing data, the memory array operable to receive a refresh address and to refresh the data stored in a memory cell located at the refresh address during a respective refresh cycle of a refresh mode;

a refresh clock circuit operable to generate a refresh clock signal having a first frequency during a first portion of the refresh mode and having a second frequency during a second portion of the refresh mode, each period of the clock signal corresponding to a respective refresh cycle, the first frequency being significantly higher than the second frequency;

a refresh address circuit coupled to the memory array and to the refresh clock circuit, the refresh address circuit operable to generate the refresh address and to update the refresh address once during each period of the refresh clock signal;

wherein the refresh clock circuit is operable to receive a clock-frequency control signal and to generate the refresh clock signal having the first frequency if the clock-frequency control signal has a first state and to generate the refresh clock signal having the second frequency if the clock-frequency control signal has a second state; and

a clock-frequency control circuit coupled to the refresh address and clock circuits, the clock-frequency control circuit operable to generate the clock-frequency control signal having the first state from the beginning of the refresh mode until the refresh address circuit has generated respective addresses for a predetermined number of memory cells, the clock-frequency control circuit operable to generate the clock-frequency control signal having the second state for a remainder of the refresh mode.

18. An integrated circuit, comprising:

a memory array including memory cells for storing data having respective signal levels, the memory array operable to receive a refresh address, the memory array also including a sense amplifier that is operable to refresh the data stored in a memory cell located at the refresh address during a respective refresh cycle by amplifying the signal level of the data and coupling the amplified signal level to the memory cell;

a refresh address circuit coupled to the memory array and operable to receive a refresh clock signal, the refresh address circuit operable to generate the refresh address and to update the refresh address during each cycle of the refresh clock signal; and

a sense-amplifier control circuit coupled to the memory array and operable to activate the sense amplifier for a respective first period of each refresh cycle during a first refresh mode and for a respective second period of each refresh cycle during a second refresh mode, the first period being long enough to allow the sense amplifier to only partially refresh the data stored in a respective memory cell, the second period being long enough to allow the sense amplifier to fully or substantially fully refresh the data stored in the respective memory cell.

19. An integrated circuit, comprising:

a memory array including memory cells for storing data having respective signal levels, the memory array operable to receive a refresh address, the memory array also including a sense amplifier that is operable to refresh the data stored in a memory cell located at the refresh address during a respective refresh cycle by amplifying the signal level of the data and coupling the amplified signal level to the memory cell;

a refresh address circuit coupled to the memory array and operable to receive a refresh clock signal, the refresh address circuit operable to generate the refresh address and to update the refresh address during each cycle of the refresh clock signal; and

a sense-amplifier control circuit coupled to the memory array and operable to activate the sense amplifier for a respective first period of each refresh cycle during a first refresh mode and for a respective second period of each refresh cycle during a second refresh mode, the first period being long enough to allow the sense amplifier to only partially refresh the data stored in a respective memory cell, the second period being long enough to allow the sense amplifier to substantially fully refresh the data stored in the respective memory cell,

wherein the sense-amplifier control circuit comprises,

a circuit having an input terminal, a feedback terminal, and an output terminal, the circuit operable to generate a sense-amplifier activation signal on the output terminal,

a first delay circuit, and

a feed-back loop coupled between the output and feedback terminals of the circuit and including a second delay circuit and a delay-select circuit serially coupled to the second delay circuit and coupled to the first delay circuit, the delay-select circuit operable to serially couple the first delay circuit to the second delay circuit during the first refresh mode and to bypass the first delay circuit during the second refresh mode.

20. An integrated circuit, comprising:

a memory array including memory cells for storing data and having refresh address and refresh duration input terminals;

a refresh address generator having a refresh clock input terminal and having refresh address output terminals respectively coupled the refresh address input terminals of the memory array;

a refresh clock circuit having a clock output terminal coupled to the clock input terminal of the refresh address generator, the refresh clock circuit operable to generate a refresh clock signal on the clock output terminal, the refresh clock signal having a first frequency during a first portion of a refresh mode and having a second frequency during a second portion of the refresh mode; and

a refresh duration circuit having a clock input terminal coupled to the clock output terminal of the refresh clock circuit and having an output terminal coupled to the refresh duration input terminal of the memory array.

21. An integrated circuit, comprising:

a memory array including memory cells for storing data and having refresh address and refresh duration input terminals;

a refresh address generator having a refresh clock input terminal, having refresh address output terminals respectively coupled the refresh address input terminals of the memory array, and having a reset input terminal;

a refresh clock generator having a clock output terminal coupled to the clock input terminal of the refresh address generator, the refresh clock generator operable to generate a refresh clock signal on the clock output terminal, the refresh clock signal having a first frequency during a first portion of a refresh mode and having a second frequency during a second portion of the refresh mode; and

a refresh duration circuit having a clock input terminal coupled to the clock output terminal of the refresh clock generator and having an output terminal coupled to the refresh duration input terminal of the memory array.

22. An integrated circuit, comprising:

a memory array including memory cells for storing data and having refresh address and refresh duration input terminals;

a refresh address generator having a refresh clock input terminal and having refresh address output terminals respectively coupled the refresh address input terminals of the memory array;

a refresh clock generator having a clock output terminal coupled to the clock input terminal of the refresh address generator, the refresh clock generator operable to generate a refresh clock signal on the clock output terminal, the refresh clock signal having a first frequency during a first portion of a refresh mode and having a second frequency during a second portion of the refresh mode; and

a refresh duration circuit having a clock input terminal coupled to the clock output terminal of the refresh clock generator, an output terminal coupled to the refresh duration input terminal of the memory array, and a refresh-mode terminal.

23. An integrated circuit, comprising:

a memory array including memory cells for storing data and having refresh address and refresh duration input terminals and including a sense amplifier coupled to the memory cells;

a refresh address generator having a refresh clock input terminal and having refresh address output terminals respectively coupled the refresh address input terminals of the memory array;

a refresh clock generator having a clock output terminal coupled to the clock input terminal of the refresh address generator, the refresh clock generator operable to generate a refresh clock signal on the clock output terminal, the refresh clock signal having a first frequency during a first portion of a refresh mode and having a second frequency during a second portion of the refresh mode; and

a refresh duration circuit having a clock input terminal coupled to the clock output terminal of the refresh clock generator and having an output terminal coupled to the refresh duration input terminal of the memory array.

24. An integrated circuit, comprising:

a memory array including memory cells for storing data and having refresh address and refresh duration input terminals;

a refresh address generator having a refresh clock input terminal and having refresh address output terminals respectively coupled the refresh address input terminals of the memory array;

a refresh clock generator having a clock output terminal coupled to the clock input terminal of the refresh address generator and having a clock-frequency input terminal, the refresh clock generator operable to generate a refresh clock signal on the clock output terminal, the refresh clock signal having a first frequency during a first portion of a refresh mode and having a second frequency during a second portion of the refresh mode;

a refresh duration circuit having a clock input terminal coupled to the clock output terminal of the refresh clock generator and having an output terminal coupled to the refresh duration input terminal of the memory array; and

a clock-frequency control circuit having an output terminal coupled to the clock-frequency input terminal of the refresh clock generator and having a refresh-mode terminal.

25. An integrated circuit, comprising:

a memory array including memory cells for storing data and having refresh address and refresh duration input terminals;

a refresh address generator having a refresh clock input terminal and having refresh address output terminals respectively coupled the refresh address input terminals of the memory array;

a refresh clock generator having a clock output terminal coupled to the clock input terminal of the refresh address generator and having a clock-frequency input terminal, the refresh clock generator operable to generate a refresh clock signal on the clock output terminal, the refresh clock signal having a first frequency during a first portion of a refresh mode and having a second frequency during a second portion of the refresh mode;

a refresh duration circuit having a clock input terminal coupled to the clock output terminal of the refresh clock generator and having an output terminal coupled to the refresh duration input terminal of the memory array; and

a clock-frequency control circuit having an output terminal coupled to the clock-frequency input terminal of the refresh clock generator, a refresh-mode terminal, and address input terminals respectively coupled to the address output terminals of the refresh address generator.

26. An integrated circuit, comprising:

a memory array including memory cells for storing data and having refresh address and refresh duration input terminals;

a refresh address generator having a refresh clock input terminal and having refresh address output terminals respectively coupled the refresh address input terminals of the memory array;

a refresh clock circuit having a clock output terminal coupled to the clock input terminal of the refresh address generator and having a clock-frequency input terminal, the refresh clock circuit operable to generate a refresh clock signal on the clock output terminal, the refresh clock signal having a first frequency during a first portion of a refresh mode and having a second frequency during a second portion of the refresh mode; and

a refresh duration circuit having a clock input terminal coupled to the clock output terminal of the refresh clock circuit and having an output terminal coupled to the refresh duration input terminal of the memory array; and

a clock-frequency control circuit having an output terminal coupled to the clock-frequency input terminal of the refresh clock generator, a refresh-mode terminal, a reset terminal, and address input terminals respectively coupled to the address output terminals of the refresh address generator.

27. An integrated circuit, comprising:

a memory array including memory cells for storing data and having address and refresh duration input terminals;

a refresh address generator having a refresh clock input terminal and having address output terminals coupled the address terminals of the memory array;

a refresh clock circuit having a clock output terminal coupled to the refresh clock input terminal of the refresh address generator; and

a refresh duration circuit having a refresh clock input terminal coupled to the clock output terminal of the refresh clock circuit and having an output terminal coupled to the refresh duration input terminal of the memory array, the refresh duration circuit operable to cause the memory array to implement a first refresh duration per refresh cycle during a first refresh mode and to implement a second refresh duration per refresh cycle during a second refresh mode, the second refresh duration being significantly different than the first refresh duration.

28. An integrated circuit, comprising:

a memory array including memory cells for storing data and having address and refresh duration input terminals;

a refresh address generator having a refresh clock input terminal and having address output terminals coupled the address terminals of the memory array;

a refresh clock circuit having a clock output terminal coupled to the refresh clock input terminal of the refresh address generator; and

a refresh duration circuit having a refresh clock input terminal coupled to the clock output terminal of the refresh clock circuit and having an output terminal coupled to the refresh duration input terminal of the memory array, the refresh duration circuit operable to cause the memory array to implement a first refresh duration per refresh cycle during a first refresh mode and to implement a second refresh duration per refresh cycle during a second refresh mode, one of the first and second refresh durations being sufficient to substantially fully refresh the data stored in a memory cell.

29. An electronic system, comprising:

a data input device;

a data output device; and

a computer circuit coupled to the data input and output devices and including a processor and a memory circuit coupled to the processor, the memory circuit including:

a memory array having memory cells for storing data, the memory array operable to fully or substantially fully refresh the data stored in a memory cell during a respective refresh cycle of a refresh mode; and

a refresh circuit coupled to the memory array, the refresh circuit operable during a first portion of the refresh mode to implement a first series of refresh cycles in the memory array at a first frequency, the refresh circuit operable during a second portion of the refresh mode to implement a second series of refresh cycles in the memory array at a second frequency that is significantly slower than the first frequency.

30. An electronic system, comprising:

a data input device;

a data output device; and

a computer circuit coupled to the data input and output devices and including a processor and a memory circuit coupled to the processor, the memory circuit including:

a memory array having memory cells for storing data, the memory array operable to refresh the data stored in a memory cell during a respective refresh cycle; and

a refresh circuit coupled to the memory array, the refresh circuit operable during a first refresh mode to implement in the memory array a refresh cycle having a refresh portion of a first duration, the refresh circuit operable during a second refresh mode to implement in the memory array a refresh cycle having a refresh portion of a second duration that is significantly longer than the first duration.

TECHNICAL FIELD

The invention relates generally to integrated circuits (ICs), and more particularly to an IC that includes an improved circuit and implements an improved method for refreshing data stored in a memory cell. Such a circuit and method allow a significant decrease in the refresh frequency, and thus a significant decrease in power consumption, while the IC is in a self-refresh mode.

BACKGROUND OF THE INVENTION

System designers continually push IC manufactures to design ICs, such as volatile-memory ICs, that have lower power requirements, particularly during low-power, i.e., "sleep", modes. Unfortunately, as discussed below, it is difficult for IC manufacturers to reduce the sleep-mode power consumed by ICs that include volatile memory cells.

Because the data stored in a volatile memory cell--such as a dynamic-random-access-memory (DRAM) cell--degrades relatively quickly, the data must be periodically refreshed. Therefore, an IC that includes one or more volatile memory cells periodically implements refresh cycles.

During a typical refresh cycle, a sense amplifier reads the data stored in the memory cell and then writes the same data back into the cell. More specifically, the cell stores a signal level, such as a voltage level, that represents the value of the stored data. For example, a voltage level of Vdd often represents a data value of logic 1, and a voltage level of ground (0 V) often represents a data value of logic 0. Unfortunately, well-known phenomena such as memory-cell leakage cause this signal level to decay over time. If this signal level is not maintained, then it may decay to a point where it represents a data value different than the data value originally stored in the memory cell. For example, a voltage level of Vdd (logic 1) may decay toward 0 V (logic 0), and if not maintained, may eventually become close enough to 0 V to represent logic 0 instead of logic 1. To maintain the stored signal level, the IC containing the memory cell implements a refresh cycle during which the sense amplifier receives the signal level from the cell, amplifies the signal level to its full value (i.e., Vdd for logic 1 and 0 V for logic 0), and provides the full signal level to the cell for storage.

During normal operation of an IC that contains a volatile memory cell, the electronic system incorporating the IC periodically issues an auto-refresh command to refresh the cell. For example, the IC may include multiple rows of memory cells and a refresh address counter that indicates the row to be refreshed. Each auto-refresh command causes the IC to implement a respective auto-refresh cycle during which the IC refreshes the cells in the addressed row and increments or decrements the counter by one. After all of the rows have been refreshed, the counter "turns over" so that the IC can continue to refresh the rows.

To insure that the system issues auto-refresh commands frequently enough to prevent the memory cells from losing their respective data, the IC manufacturer specifies the maximum refresh period that can elapse between successive refreshes of a memory cell. For example, suppose that the IC must refresh each memory cell at least once every 64 milliseconds (ms), includes 4,096 (4 k) rows of memory cells, and refreshes an entire row during each refresh cycle. Then, to insure that no memory cells lose their respective data, the system must execute at least 4,096 auto-refresh commands (one for each row) every 64 ms. The system can issue these auto-refresh commands all at once (burst auto refresh), or can distribute them over the 64 ms refresh period (distributed auto refresh).

Furthermore, to insure that the refresh cycles are long enough to allow the IC to adequately refresh a memory cell, the IC manufacture specifies the minimum duration that the system must allow for each refresh cycle. Therefore, once the system issues an auto-refresh command, it must wait at least this minimum duration before issuing another command to the IC. For example, if the IC takes 70 nanoseconds (ns) to implement a refresh cycle, then the system must wait at least 70 ns after issuing an auto-refresh command before issuing another command to the IC.

To increase the speed rating--and thus the price--of the IC, the manufacturer often specifies the shortest possible duration for each refresh cycle. Often, this duration is too short to allow the IC to refresh a memory cell to its full signal level. As discussed below, this may require the IC manufacturer to specify a shorter refresh period between successive refreshes of a memory cell. Also as discussed below, a shorter refresh period requires the memory to issue internal refresh commands more frequently during the self-refresh mode, and thus may cause the IC to draw more power during a self-refresh mode.

FIG. 1 is a plot of the broken-line charge/discharge curves 10 and 12 for a memory cell that the IC only partially refreshes. That is, the IC implements a refresh cycle that is too short to allow the memory cell to acquire a full signal level. In this example, Vdd/2 is the threshold level between logic 1 and logic 0. Referring to the curve 10, at time t1, a memory cell storing a logic 1--which here corresponds to Vdd--is coupled to the respective digit line to begin the refresh cycle. Because the digit line is capacitive, the cell voltage drops and the digit-line voltage--which is represented by the solid curve 11--rises to a starting voltage Vs1. Furthermore, because the digit-line capacitance is approximately five times greater than the cell capacitance, the cell voltage drops more than the digit-line voltage rises. Starting at time t2, the IC charges the memory cell over a refresh time Trefresh. Typically, Trefresh is a portion of the total refresh-cycle time. For example, if the refresh-cycle time is 70 ns, Trefresh may be 60 ns. As shown, Trefresh isn't long enough for the IC to fully charge the memory cell to Vdd. Consequently, the IC can only partially charge the memory cell to V1, which is lower than Vdd. For example, V1 may be 100-300 millivolts (mV) lower than Vdd. After Trefresh elapses, the memory cell discharges to Vdd/2 over a discharge time Tdischarge, which is proportional to V1. Thus, the higher V1, the longer Tdischarge, and the lower V1, the shorter Tdischarge. The shorter Tdischarge, the more frequently the IC must refresh the signal level stored in the memory cell, and thus the shorter the maximum refresh period that the IC manufacturer can specify. A similar analysis applies to the curves 12 and 13, which corresponds to the memory cell storing logic 0.

During low-power operation of the system such as during a "sleep" mode, the system issues a self-refresh command that causes the IC to enter a self-refresh mode. During a self-refresh mode--which is typically a low-power mode of the IC--the IC typically ignores all system commands (other than a "wake-up" command) and performs few if any functions other than automatically refreshing the memory cells. Because it ignores auto-refresh commands during the self-refresh mode, the IC includes self-refresh circuitry that automatically implements self-refresh cycles during the self-refresh mode. Except for the automatic implementation, the self-refresh cycles are similar to auto-refresh cycles.

FIG. 2 is a plot of the peak and average currents that the IC draws during a self-refresh mode. The peak current Ipeak is the total refresh current that the IC draws during a respective self-refresh cycle to recharge the memory cell or cells being refreshed. Each self-refresh cycle has the refresh time Trefresh during which the IC draws the refresh current. And in this example, the self-refresh cycles are evenly distributed throughout the self-refresh period, one every Trefper seconds. For example, Trefresh=60 ns and Trefper=20 microseconds (.mu.s). The average current lavg is proportional to Ipeak, Trefresh, and the IC's power consumption, and is inversely proportional to Trefper.

To save power in the self-refresh mode, the IC designers often reduce the average current lavg by designing the IC to implement the longest possible self-refresh period between successive self-refreshes of a memory cell. Typically, the designers can lengthen the self-refresh period beyond the specified auto-refresh period, and thus can lengthen Trefper beyond the maximum time specified between evenly distributed auto-refresh cycles. For example, using the above values, if the specified maximum auto-refresh period is 64 ms, then an evenly distributed auto refresh requires one auto-refresh cycle every (64 ms/4096 rows)=15.6 .mu.s. The designers, however, may design the IC such that the self-refresh period is approximately 82 ms, which corresponds to Trefper.about.20 .mu.s during a self-refresh mode.

Unfortunately, because during normal operation the short auto-refresh cycles prevent the IC from fully refreshing the stored data, the IC designers cannot further lengthen Trefper without risking data corruption during the self-refresh mode.

SUMMARY OF THE INVENTION

In one aspect of the invention, an IC includes a memory array having memory cells for storing data. The memory array refreshes the data stored in each memory cell during a respective refresh cycle of a refresh mode. The IC also includes a refresh circuit that is coupled to the memory array, that during a first portion of the refresh mode implements a first series of refresh cycles in the memory array at a first frequency, and that during a second portion of the refresh mode implements a second series of refresh cycles in the memory array at a second frequency.

In another aspect of the invention, an IC includes a memory array and refresh circuit. During a first refresh mode, the refresh circuit implements in the memory array a refresh cycle having a refresh portion of a first duration, and during a second refresh mode the refresh circuit implements a refresh cycle having a refresh portion of a second duration.

Thus, such an IC can achieve a high-speed rating by implementing relatively fast auto-refresh cycles during normal operation and can achieve power savings during a self-refresh mode by implementing longer Trefper times between self-refresh cycles.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graph of the charge/discharge curves for a memory cell that is only partially refreshed during a conventional refresh cycle.

FIG. 2 is a graph of the peak and average currents drawn by a conventional IC during a self-refresh mode.

FIG. 3 is a block diagram of a refresh circuit and a memory array according to an embodiment of the invention.

FIG. 4 is a graph of the charge/discharge curves for a memory cell that is refreshed by the refresh circuit of FIG. 3 during a self-refresh mode.

FIG. 5 is a graph of the peak burst, peak maintenance, and average currents drawn during a self-refresh mode by an IC that includes the refresh circuit of FIG. 3.

FIG. 6 is a timing diagram for an embodiment of the refresh circuit of FIG. 3.

FIG. 7 is a schematic diagram of an embodiment of the reset circuit of FIG. 3.

FIG. 8 is a schematic diagram of an embodiment of the frequency-control circuit of FIG. 3.

FIG. 9 is a schematic block diagram of an embodiment of the refresh clock generator of FIG. 3.

FIG. 10 is a timing diagram for an embodiment of the refresh clock generator of FIG. 9.

FIG. 11 is a schematic block diagram of an embodiment of the sense-amplifier control circuit of FIG. 3.

FIG. 12 is a block diagram of an embodiment of a memory circuit that includes the refresh circuit and memory array of FIG. 3.

FIG. 13 is a block diagram of an embodiment of an electronic system that includes the memory circuit of FIG. 12.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3 is a block diagram of refresh circuit 20 for implementing a self-refresh mode in a memory array 22. Typically, the circuit 20 and the array 22 are part of an IC that receives a SELF-REFRESH signal from the system in which it is installed. The circuit 20 implements a self-refresh mode that has an initial burst portion to fully refresh all of the memory cells in the array 22 and that has a subsequent maintenance portion to refresh the cells at the maximum possible self-refresh period. Thus, as discussed below, the circuit 20 allows a significant increase in Trefper (FIG. 2), and thus provides a significant power savings, during the maintenance portion of the self-refresh mode.

The circuit 20 includes a reset circuit 24 for generating a REFRESH signal in response to SELF-REFRESH.

A refresh clock-frequency control circuit 26 generates a FREQUENCY CONTROL signal that has a first state during the initial burst portion of the self-refresh mode and that has a second state during the subsequent maintenance portion of the self-refresh mode. A refresh clock generator 28 generates a CLOCK signal that has a relatively high burst frequency during the burst portion of the self-refresh mode and a relatively low maintenance frequency during the maintenance portion. The CLOCK signal, however, is not the same as the external clock signal received by the IC that incorporates the refresh circuit 20. Therefore, "CLOCK" refers to the signal generated by the generator 28 unless stated otherwise.

A refresh address generator 30 addresses the memory cell, row of memory cells, or column of memory cells to be refreshed during a respective self-refresh cycle. In one embodiment, the generator 30 is a counter that resets to an initial address at the beginning of the self-refresh mode and then increments/decrements the address once during each period of CLOCK.

A sense-amplifier control circuit 32 controls the length of the Trefresh (FIG. 1 and FIG. 4) time during self-refresh to allow full refresh of the memory cells in the array 22. In some embodiments, the control circuit 32 may also control the length of the Trefresh time during auto-refresh, and may control the sense-amplifier on time during read and write cycles. Specifically, during a self-refresh mode, the control circuit 32 activates the respective ones of the sense amplifiers 34 in the memory array 22 for a predetermined Trefresh time during each self-refresh cycle Trefper. Trefper is synonymous with the self-refresh cycle in this disclosure. In one embodiment, the control circuit 32 activates the respective sense amplifiers 34 for a Trefresh time of approximately 80 ns during each Trefper such that these sense amplifiers have sufficient time to fully refresh the respective memory cells. In an embodiment where the control circuit 32 also controls the length of the Trefresh time during an auto-refresh cycle, the control circuit 32 activates the sense amplifiers 34 for a Trefresh time that is significantly shorter than the Trefresh time during the self-refresh mode. For example, the auto-refresh Trefresh time may be 60 ns, which may be insufficient to allow the sense amplifiers 34 to fully refresh the respective memory cells. This shorter auto-refresh Trefresh time, however, allows the IC to achieve a higher speed rating by decreasing the auto-refresh cycle time. That is to say, the auto-refresh is completed sooner and the IC is ready for a new instruction.

FIG. 4 is a graph of charge/discharge curves 34 and 36 for a memory cell of the array 22 (FIG. 3) that is fully refreshed during a self-refresh cycle implemented by the refresh circuit 20 (FIG. 3). Fully refreshing the memory cell significantly increases Tdischarge, and thus allows the refresh circuit 20 to significantly increase the distributed self-refresh refresh Trefper during the maintenance portion of the self-refresh mode.

FIG. 5 is a graph of the peak current Ipeak during the burst and maintenance portions of the self-refresh mode implemented by the circuit 20 (FIG. 3) and the average current lavg during the maintenance portion. During the initial bu