A method and apparatus for sequencing the execution of a simulation system comprising at least two subsystem simulators. The simulation system further comprises a first and second simulator, a processor for executing program instructions of a control program stored in a memory coupled to the processor, a router for coupling first simulator inputs and outputs to second simulator outputs and inputs respectively, and an input device including a control and monitor panel for controlling said sequencing. The control program controls a plurality of subsystem simulators and comprises an initiation sequence for initiating execution of a first simulator at an initiation time including defining a first simulator output state, a first execution sequence wherein said first simulator executes a simulation and updates first simulator outputs to said second simulator, a first halt sequence for halting said first execution sequence, a first transfer sequence for transferring first simulator output data to said second simulator inputs, a second execution sequence wherein said second simulator executes a simulation after said first simulator execution has halted, a second halt sequence for halting said second execution sequence at a second halt time equal to the earlier of said first halt time and a change in state of said second simulator outputs, a repeat sequence for restarting said first execution sequence to run until a final simulation time is reached, and a back-up sequence for restarting the first execution sequence at a last verified simulation time.
The procedure and system of the invention are used to implement a technical application from which all uncontrolled internal interdependencies have been eliminated. The functional assemblies contained in the application are normalized so that the input data of each functional assembly unambiguously and alone determines the output data produced by the assembly. Further, according to the invention, the elements contained in the functional assemblies are normalized so that the input data of the elements unambiguously and alone determines the output data. There may be one or more elements or functional assemblies. Further, a functional assembly may form other functional assemblies. In an embodiment of the invention, the application implemented is a part of a telephone exchange software application in which the functional assemblies and elements are of an algorithmically processing type.
A system and method of verifying an electronic system. A verification kernel is provided and the electronic system is expressed as a logic design. A wrapper is defined, wherein the wrapper is an interface between the logic design and the verification kernel. Tests to be run against the logic design are placed within a diagnostic program and an interface between the diagnostic program and the verification kernel is defined. The tests are then executed against the logic design. The results of the tests are captured and validated against expected results.
A method, apparatus, and computer-readable media for managing an event queue for a simulation comprising a plurality of events each scheduled to occur at one of a plurality of event times comprises generating a sorted tree data structure comprising a plurality of nodes, wherein each of the nodes in the sorted tree data structure corresponds to only one of the event times, and wherein the nodes of the sorted tree data structure are sorted according to the event times of the nodes; generating an event record for each event; and associating the event records with the nodes so that each of the event records is associated with the node corresponding to the event time at which the respective event is scheduled to occur.
In the simulation of an analog and mixed-signal analog-digital physical circuit, events are assigned scheduled times. The events are stored in buckets in a hash table, with the scheduled times of the events in each bucket associated with the bucket. The scheduled times are organized into a heap, with the earliest scheduled time at the root of the heap. The earliest scheduled time is removed from the heap, and the events in the associated bucket are performed. Performing the scheduled events can cause new events to be scheduled, and existing events to be de-scheduled. When all the events in the bucket associated with the earliest scheduled time are simulated, the remaining scheduled times are re-organized into a new heap, and the steps of removing the earliest scheduled time, performing the scheduled events, and re-organizing the remaining scheduled times are repeated.
A system, method and computer program features of the present invention, relate to verification or simulation of a design using a behavioral model structure for use in a Client/Server configuration. A physical part presents the external interface, and a functional procedural part which is comprised of at least one VHDL process. A testcase is a set of procedure calls written in VHDL. The present invention describes the architecture and implementation of a client/server behavioral model and procedural approach for testcase development which results in significant gain in productivity, quality of logic verification, and portability.
