An integrated circuit, a programming mechanism and a method are provided for programming test information upon non-volatile storage devices of the integrated circuit. The test information includes a pass/fail outcome arising from one or more test operations to which the integrated circuit is exposed. In addition to or in lieu of the test outcomes, test results of one or more parametric tests at select test operations can be measured from and programmed back into the integrated circuit. Test limits against which the test results can be compared may also be programmed into the integrated circuit. The test outcomes of various test operations, test results of various test parameters and test limits of the same or dissimilar test parameters are stored in separate non-volatile storage locations attributed to the integrated circuit. Those storage locations and, particularly, the bits contained therein are read either before the integrated circuit is packaged, after it is packaged, or after the packaged integrated circuit is shipped to customer. Programming test information as to that particular integrated circuit provides traceability of test operations performed, quality control of integrated circuits shipped, failure analysis of integrated circuits manufactured and, in some instances, lessened overall test time.
RELATED APPLICATION
This application is related to a co-pending U.S. Patent Application Ser. No. 09/050,243 to Chhor entitled "Circuitry, Apparatus and Method for Embedding Quantifiable Test Results Within a Circuit Being Tested" which is incorporated as if fully set forth herein.
A method is provided for programming and reading manufacturing information upon non-volatile storage elements of the integrated circuit. The manufacturing information includes the particular processing recipe and layout of the integrated circuit, each recipe or layout indicative of a specific hardware revision. The storage elements may be programmed prior to assembling the integrated circuit within a semiconductor package, and the programmed elements are read prior to shipping the packaged integrated circuit to a customer. If the read hardware revision is not qualified for release, the product will be placed in a staging area and prevented from shipping to a customer or end user. Thus, the programmed hardware revision serves to gate product at test before shipping that product to a customer. The manufacturing information is programmed by the manufacturer and is inaccessible by a customer since the address space which contains product engineering bits is known only to the manufacturer.
A system for identifying and sorting integrated circuit devices based on an encrypted Fuse ID information such as manufacturing and test information stored in the integrated circuit device, includes a test fixture for receiving an integrated circuit device to be identified and sorted. The system further includes a portable, user friendly processor communicatively coupled to the test fixture to read the stored encrypted device identification data from the integrated circuit device and decrypt the read encrypted Fuse ID information, and to compare the decrypted device identification data to a previously entered sort criteria and to identify and sort the integrated circuit device based on the outcome of the comparison.
An electronics module is assembled by demountably attaching integrated circuits to a module substrate. The module is then tested at a particular operating speed. If the module fails to operate correctly at the tested speed, the integrated circuit or circuits that caused the failure are removed and replaced with new integrated circuits, and the module is retested. Once it is determined that the module operates correctly at the tested speed, the module may be rated to operate at the tested speed and sold, or the module may be tested at a higher speed.
An electronics module is assembled by demountably attaching integrated circuits to a module substrate. The module is then tested at a particular operating speed. If the module fails to operate correctly at the tested speed, the integrated circuit or circuits that caused the failure are removed and replaced with new integrated circuits, and the module is retested. Once it is determined that the module operates correctly at the tested speed, the module may be rated to operate at the tested speed and sold, or the module may be tested at a higher speed.
