Upon opening a tunnel window of an EEPROM having a floating gate, a portion of a conductive layer which serves as a floating gate electrode is cut as an opening and side walls are formed on side portions of the opening. A gate insulating film is removed by a self-aligned method using each side wall as a mask, and a thin tunnel oxide is locally formed within the tunnel window.
There is provided a method of manufacturing a semiconductor device including a nonvolatile memory including forming an element isolation area surrounding an element area in a semiconductor substrate doped with a first type conductive impurity, forming a gate insulating film on the element area, forming selectively a cap film on the gate insulating film, burying selectively with a mask film surrounding the cap film on the gate insulating film, forming a tunnel window by removing selectively the cap film, forming an impurity diffusion layer in a surface region of the semiconductor substrate underneath the gate insulating film by introducing a second type conductive impurity using the mask film as a mask, removing the gate insulating film in the tunnel window, forming a tunnel insulating film in the tunnel window, forming a floating gate electrode film, an inter-gate electrode film, and a control gate electrode film on the tunnel insulating film, and forming a source-drain in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the control gate electrode film by introducing the second type conductive impurity into the surface region using the control gate electrode film as a mask.
A manufacturing process including: forming a first insulating region on top of an active area; forming a tunnel region at the side of the first insulating region; depositing and defining a semiconductor material layer using a floating gate mask to form a floating gate region. The floating gate mask has an opening with an internal delimiting side extending at a preset distant from a corresponding outer delimiting side of the mask, so that the floating gate region forms inner a hole, and the tunnel region is defined, as regards its length, by the floating gate ask alone. The hole is filled with a dielectric material layer. The surface of the floating gate region is planarized, and an insulating region of dielectric material is made. A control gate region and conductive regions in the active area are then formed.
