A test system for SRAM uses two mechanical probes to contact the bit lines of a column of SRAM storage cells. A word line is selected and a voltage is applied through the first mechanical probe to the first bit line forcing the second and complementary bit line to have a conducting FET coupled via contacts and a section of the second bit line to the second mechanical probe. A variable voltage is applied to the second mechanical probe and the corresponding resulting currents are measured. The first and second mechanical probes are then reversed and the process repeated. The voltage versus current from the second mechanical probe determines electrical characteristics of the contacts of the SRAM bit cell. The resulting data determining the electrical characteristics of the SRAM contacts are used to control process parameters during manufacture, set process parameters during manufacturing development, and to aid in failure analysis of manufactured SRAM bit cells.
A system and method are disclosed herein for leakage testing of a static random access memory (SRAM) semiconductor memory device. Subtle leakage defects may be present in some devices in the early stages of SRAM production. These defects may later result in hard failures when packaged devices are burned in, but are not detected by functional tests performed during wafer sort. The leakage defects are associated with complementary bit line pairs within the SRAM matrix, and may be revealed by leakage current measurements made between all of the complementary bit line pairs within the SRAM. Comparatively minor modifications to the internal circuitry of the SRAM enable the leakage measurements to be performed during wafer sort, so defective devices can be screened out prior to packaging, lead-bonding, etc.
This invention is about a system for diagnosing memory cells in a memory module. A first multiplexer module selectively connects a diagnosis signal in response to a multiplexer control signal to a data line associated with a predetermined memory cell. A second multiplexer module connects the data line to the predetermined memory cell via the bit line in response to a bit selection signals. Similarly, a complement diagnosis signal may be connected to a predetermined memory cell via the complement data line and bit line through the same control and bit select signals. A pair of access pads are provided for passing the diagnosis signal and the complement diagnosis signal for external accessing.
An integrated circuit contains a static memory cell with a pair of cross-coupled inverters. The outputs of the inverters are coupled to bitlines the main current channels of access transistors. The integrated circuit operates in a normal mode and in a test mode. In the test mode the conductivity of the access transistors is made relatively higher in proportion to the drive strength of the memory cell while substantially equal voltages are applied to the bitlines (for example by applying a voltage to the wordline that makes the access transistors more conductive than during access in the normal mode). An error is detected when this causes the state of the cell to flip.
