A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
The inventive control logic provides the selection signals for a bi-endian rotator MUX. The logic determines the starting point for the data transfer by determining which input register byte is going to Byte 0 of the output register. The control logic passes the starting point to single decoder. The decoded value is then sent to a plurality of MUXs, one for each of the output register bytes. Each of the MUXs is prewired to receive a portion of bits of the decoded value, and the portion is arranged in a particular order. The MUXs then send their respective outputs to the rotator MUX as selection control signals.
An apparatus for and a method of ensuring that a non-speculative instruction is not fetched into an execution pipeline, where the non-speculative instruction, if fetched, may cause a cache miss that causes potentially catastrophic speculative processing, e.g., speculative transfer of data from an I/O device. When a non-speculative instruction is scheduled for a fetch into the pipeline, a translation lookaside buffer (TLB) miss is made to occur, e.g., by preventing the lowest level TLB from storing any page table entry (PTE) associated with any of the non-speculative instructions. The TLB miss prevents the occurrence of any cache miss, and causes a micro-fault to be injected into the pipeline. The micro-fault includes an address corresponding to the subject non-speculative instruction, and when it reaches the end of the pipeline, causes a redirect of instruction flow of the pipeline to the address, and thus the non-speculative instruction is fetched and executed in a non-speculative manner.
One embodiment of the present invention provides a system that facilitates marking of objects defined within an object-oriented programming system to keep track of accesses to fields within the objects. The system operates by receiving a reference to a field within an object, and identifying a marking bit within the object that is associated with the field. Note that each marking bit within the object is associated with a different subset of fields within the object. Next, the system sets the marking bit to indicate that at least one field within the associated subset of fields has been referenced. Finally, the system performs the reference to the field. In one embodiment of the present invention, the object includes N marking bits numbered 0, 1, 2, . . . , N-1 and M fields numbered 0, 1, 2, . . . , M-1. In this embodiment, the system identifies the marking bit associated with the field by starting with a field number for the field, and applying a modulo N operation to the field number to produce a number for the associated marking bit. In a variation on this embodiment, N is a power of two.
