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Description  |
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TECHNICAL FIELD OF THE INVENTION
The present invention relates to network interfacing and more particularly,
to methods and systems controlling network data traffic on media of
full-duplex networks.
BACKGROUND ART
Local area networks use a network cable or other media to link stations on
the network. Each local area network architecture uses media access
control (MAC) enabling network interface cards at each station to share
access to the media.
A full duplex environment has been proposed for Ethernet networks, referred
to as IEEE 802.3x, Full Duplex with Flow Control-Working Draft (0.3). The
full duplex environment provides a two-way, point-to-point communication
link between two network elements, for example a network station and a
switched hub. Hence, two or more stations can simultaneously transmit and
receive Ethernet data packets between each other via a switched hub
without collisions.
Full-duplex operation does not require that transmitters defer, nor that
they monitor or react to receive activity, as there is no contention for a
shared medium in this mode. Full-duplex operation can be used when the
physical medium is capable of supporting simultaneous reception and
transmission (fibre or copper), there are exactly two stations on the link
and both stations have been configured to use full duplex links. The most
common configuration envisioned for full-duplex operation consists of a
multiport bridge (a switch) with dedicated point-to-point connections to
several end-stations.
Network congestion occurs if a receiving network element is unable to
receive data at a rate greater than or equal to the transmission rate of
the transmitting element. For example, traffic in a client-server
environment is dominated by client requests followed by a burst of frames
from the server to the requesting client. Although the full duplex
environment enables the server to transmit packets while receiving
requests from other clients, only a limited number of client requests can
be output to the server from the switched hub at the assigned switching
port. If the number of client requests exceeds the capacity of the
server's port, some of the data packets will be lost. Alternatively, a
client having limited buffer space may be unable to keep up with the
transmission rate of the server, resulting in lost packets.
Flow control has been proposed to reduce network congestion, where a
sending station temporarily suspends transmission of data packets. A
proposed flow control arrangement for a full duplex environment, referred
to as IEEE 802.3x[2], specifies generation of a flow control message, for
example a PAUSE frame. A transmitting station that receives the PAUSE
frame enters a pause state in which no frames are sent on the network for
a time interval specified in the PAUSE frame. The PAUSE frame relieves
congestion at the receiver. For example, in a switch with several 10 Mbps
or 100 Mbps full-duplex ports, it is possible for the traffic from all the
ports to overload the switch. In these periods, the switch will transmit
PAUSE frames to those 10 Mbps or 100 Mbps ports that the switch believes
are the source of the congestion. These stations will stop transmitting
frames for the period specified by the PAUSE frame, thus relieving
congestion at the switch.
The round-trip link delay between the switch and the end station has
importance in times of congestion. If the link delay between the switch
and the end station is long, and the bandwidth of the link is high, the
transmission of a PAUSE frame after congestion is detected will not have
effect until at least one round-trip link delay's worth of data has
entered the switch. Similarly, when congestion is relieved and the switch
transmits a PAUSE frame with value 0 (allowing station transmission), it
will be at least one round-trip delay before data flows into the switch
again.
SUMMARY OF THE INVENTION
There is a need for an arrangement that determines when to initiate flow
control by a network element, taking into account the latency of a link,
i.e., the round-trip delay of a point-to-point full-duplex connection.
These and other needs are met by the present invention which provides a
method of determining a link latency between stations on a network, in
which a physical layer of a remote station is placed into a remote
loopback configuration so that all data received from the network is
transmitted back onto the network. A specified data pattern is transmitted
from a local station to the remote station. At the local station the
specified data pattern that has been transmitted back onto the network by
the remote station is detected. The link latency between the local station
and the remote station is then determined as a function of the time
elapsed between the transmitting of the specified data pattern from the
local station and the detecting of the specified data pattern at the local
station.
The earlier stated needs are also met by another embodiment of the present
invention which provides a method of controlling a remote station on a
network, in which a remote loopback control signal is transmitted from a
local station to a remote station. At the remote station, the reception of
the remote loopback control signal is detected. The remote station is
configured in response to the reception of the remote loopback control
signal such that all data received from the network is transmitted back
onto the network.
The earlier stated needs are also met by a still further embodiment of the
present invention which provides a method of controlling congestion at a
local station in a network, comprising the steps of placing a physical
layer of a remote station into a remote loopback configuration such that
all data received from the network is transmitted back onto the network. A
specified data pattern is transmitted from a local station to the remote
station. The specified data pattern that has been transmitted back onto
the network by the remote stations detected at the local station. The link
latency between the local station and the remote station is then
determined as a function of the time elapsed between the transmitting of
the specified data pattern from the local station and the detecting of the
specified data pattern at the local station. A congestion relieving signal
is then transmitted from the local station to the remote station as a
function of the determined link latency.
The earlier stated needs are also met by another embodiment of the present
invention which provides a physical layer device connecting a station to a
network, comprising a transmit side which transmits data from the station
onto the network, a receive side which receives data from the network and
provides the data to the station, and a configurable internal routing
arrangement remotely controllable in response to a remote loopback
configuration signal received from the network to couple the receive side
to the transmit side such that all data received from the network is
transmitted directly back onto the network.
The foregoing and other features, aspects and advantages of the present
invention will become more apparent from the following detailed
description of the present invention when taken in conjunction with the
accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a network interface according to an embodiment
of the present invention.
FIG. 2 is a diagram illustrating a network configuration of stations having
the network interface of FIG. 1.
FIG. 3 is a flow diagram illustrating a method of controlling transmission
of data packet according to an embodiment of the present invention.
FIG. 4 is a flow diagram illustrating flow control in a full duplex
network.
FIGS. 5A, 5B and 5C are flow diagrams illustrating alternative methods for
initiating flow control for selected time intervals.
FIGS. 6A and 6B are diagrams illustrating the methods of FIGS. 5A and 5B
for calculating a flow control time interval, respectively.
FIG. 7 is a block diagram of the media access control (MAC) of FIG. 1.
FIG. 8 is a block diagram of a full-duplex link.
FIG. 9 is a block diagram of a full-duplex link in remote loopback
configuration mode in accordance with an embodiment of the present
invention.
FIG. 10 is a flow chart of a method of determining the link latency of a
link, in accordance with an embodiment of the present invention.
FIG. 11 is a block diagram of a physical layer device constructed in
accordance with an embodiment of the present invention.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
The following description provides an exemplary embodiment of a network
arrangement that makes use of the determination of the latency of a
network link according to embodiments of the present invention. This
network arrangement and the described use of the determined link latency
are exemplary only, however, as other examples of network arrangements and
uses of the determined link latency are contemplated without departing
from the spirit and scope of the present invention.
FIG. 1 is a block diagram of an exemplary network interface 10 of a network
station that accesses the media of an Ethernet (ANSI/IEEE 802.3) network
according to an embodiment of the present invention.
The network interface 10, preferably a single-chip, 32-bit Ethernet
controller, provides an interface between a local bus 12 of a computer,
for example, a peripheral component interconnect (PCI) local bus, and an
Ethernet-based media 50. An exemplary network interface is the Am79C971
PCnet-FAST Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus,
disclosed in Preliminary Data Sheet Publication #20550, Rev. B, Issue Date
May, 1996, from Advanced Micro Devices, Inc., Sunnyvale, Calif., the
disclosure of which is incorporated in its entirety by reference.
The interface 10 includes a PCI bus interface unit 16, a direct memory
access (DMA) buffer management unit 18, and a network interface portion
20. The network interface portion 20 selectively operates in either
half-duplex mode or full-duplex mode according to IEEE 802.3x[2]. The
network interface portion 20 includes a media access control (MAC) core
22, a General Purpose Serial Interface (GPSI) 23a, a Media Independent
Interface (MII) 23b for connecting external 10 MBit/s or 100 MBit/s
transceivers, an External Address Detection Interface (EADI) 23c, an
attachment unit interface (AUI) 24, and a twisted-pair transceiver media
attachment unit (10BASE-T MAU) 26. The AUI port 24 follows the
specification ISO/IEC 8802-3 (IEEE-ANSI 802.3). The interface 10 also
includes an EEPROM interface 28, an LED control 29, and an expansion bus
interface 31 for boot RAM (e.g., EPROM or Flash memory) during startup,
and an IEEE 1149.1-compliant JTAG Boundary Scan test access port interface
36. Full-duplex operation can be performed by any of the AUI, GPSI,
10BASE-T and MII interfaces. Additional details of these interfaces are
disclosed in the above-referenced Am79C971 Preliminary Data Sheet.
The network interface 10 also includes a PCI bus receive first in first out
(FIFO) buffer 30a, a MAC receive FIFO buffer 30b, a PCI bus transmit FIFO
buffer 32a, a MAC transmit FIFO buffer 32b, and a FIFO controller 34. As
shown in FIG. 1, the MAC receive FIFO buffer 30b effectively passes stored
data bytes to the PCI bus receive FIFO buffer 30a when the expansion bus
interface 31 is not in use.
The PCI bus interface unit 16, compliant with the PCI local bus
specification (revision 2.1), receives data frames from a host computer's
CPU via the PCI bus 12. The PCI bus interface unit 16, under the control
of the DMA buffer management unit 18, receives DMA and burst transfers
from the CPU via the PCI bus 12. The data frames received from the PCI bus
interface unit 16 are passed on a byte-by-byte basis to the PCI bus
transmit FIFO buffer 32a, and subsequently to the MAC transmit FIFO buffer
32b.
The buffer management unit 18 manages the reception of the data by the PCI
bus interface unit 16 and retrieves information from header bytes that are
transmitted at the beginning of transmissions from the CPU via the PCI bus
12. The header information identifying the byte length of the received
frame is passed to the FIFO control 34.
The Manchester encoder and attachment unit interface (AUI) 24 includes a
Collision In (CJ+/-) differential input pair, operating at pseudo ECL
levels, that signals to the network interface 10 when a collision has been
detected on the network media. A collision occurs when the CI inputs are
driven with a 10 MHz pattern of sufficient amplitude and pulse width that
meets the ISO/IEC 8802-3 (ANSI/IEEE 802.3) standards. The Data Out (DO+/-)
output pair of the AUI 24 transmits Manchester encoded data at pseudo ECL
levels onto the network media 50. Similarly, the twisted pair interface 26
includes 10BASE-T port differential receivers (RXD+/-) and 10BASE-T port
differential drivers (TXD+/-).
The media access control (MAC) 20 performs the CSMA/CD functions in
response to signals from the interfaces 24 or 26. For example, carrier
sense is detected by the DI and RXD signal paths of the AUI port 24 and
MAU 26, respectively. The AUI 24 and the MAU 26 each include a physical
layer that senses idle to non-idle transitions on the media 50, as
specified in Ethernet (ANSI/IEEE 802.3) protocol. The detection of
activity on the media 50 is performed by the physical layer, which asserts
a valid receive data indication to the MAC 20 layer in response to the
detection and decoding of the preamble of a received data packet. Hence,
the term activity on the media refers to reception of valid data. The
sensed deassertion of the receive carrier occurs when the physical layer
determines that the media 50 transitions from a nonidle to an idle state.
The AUI 24 detects a collision by the CI inputs, and the MAU 26 detects a
collision by sensing activity on both twisted pair signals RXD and TXD.
As described below, data packets received from the media 50 are processed
by the MAC 22 to recover the payload data carried by the data packets.
Once the MAC 22 recovers the payload data of the data packets, the MAC 22
stores the data bytes of the payload data into the MAC receive FIFO buffer
30b under the control of the FIFO control 34. The data bytes stored in the
MAC receive FIFO buffer 30b are passed to the PCI bus receive FIFO buffer
30a and then the PCI bus interface unit based on the bus latency and burst
size for the PCI bus 12. The network interface 10 includes a MAC pause
controller 38, and wait time registers/counters 40 that identify
thresholds for initiating flow control commands (i.e., PAUSE commands) by
the MAC 22 and/or the FIFO controller 34. The MAC pause controller 38
monitors the input storage rate for data bytes received by the MAC 22 into
the MAC receive FIFO buffer 30b based on write messages supplied to the
MAC Pause Controller 38 from the MAC 22. The MAC pause controller 38 also
monitors the rate of data output from the MAC receive FIFO buffer 30b
based on read messages, bus latency information, and burst size
information from the PCI Bus Interface Unit 16.
The MAC Pause Controller 38 determines whether to initiate a flow control
mode based on the number of data bytes stored in the receive buffer. The
MAC Pause Controller 38 also determines the duration of the flow control,
referred to as the wait time, and includes internal counters to monitor
the duration of the wait time.
FIG. 2 is a diagram illustrating a network 42 having network elements 44
and 46 connected by a network media 50. The term network element refers
generically to the network stations 44 and the hub 46. Each of the network
stations 44 include the network interface 10 of FIG. 1. The network
element 46 is a switched hub that includes a MAC controller and an
internal data buffer storing data packets as data bytes before
transmission to a network station 44. The media 50 may be either fiber
optic, twisted pair wire, or coaxial, and hence may couple the interface
10 of each corresponding station 44 to 10BASE-T, 10BASE-2, 100BASE-TX,
100BASE-T4, or 100BASE-FX networks. The network 42 may operate at 10
megabits per second (10 Mbit/s), 100 megabits per second (100 Mbit/s), or
1000 megabits per second (1000 Mbit/s).
As shown in FIG. 2, the media 50 are connected to a hub 46. Since the
network of FIG. 2 is implemented as a full-duplex network, the hub 46 is
implemented as a switch. Full-duplex is defined as the capability of a
network element 44 and 46 to simultaneously transmit and receive data
packets on the corresponding media 50. Hence, CSMA/CD functions are
disabled in a full-duplex network, such that controllers do not use
carrier sense to defer to passing traffic, and do not use collision detect
to abort, backoff, or retry transmissions.
An example of full-duplex communication in the network 42 of FIG. 2
involves point-to-point transmission between stations A and B via the hub
46. The hub 46 itself includes full-duplex capabilities, enabling stations
A and B to each simultaneously transmit and receive data. In addition,
stations A and B may simultaneously send data to station E, which
simultaneously sends acknowledgment messages to stations A and B. Hence,
full-duplex communication occurs between station A and the hub 46, station
B and the hub 46, and station E and the hub 46. Alternatively, full duplex
operation is also possible in the special case of two stations with no
hub.
The hub 46 is a switch capable of performing auto-negotiation with the
respective network stations 44, including a link start-up procedure each
time a link to a station 44 is connected, powered on or reset. During
auto-negotiation, the hub 46 automatically configures each station 44 for
operating according to the network configuration parameters, for example,
network topology, signaling, distance to hub, and number of stations on
the network.
Upon completion of the auto-negotiation process by the hub 42, the network
interface 10 in each station 44 will receive and store network
configuration data, described below. Additional details regarding
repeaters and auto-negotiation are disclosed in Breyer et al. "Switched
and Fast Ethemet: How It Works and How to Use It", ZiffDavis Press,
Emeryville, Calif. (1995), pp. 60-70, and Johnson, "Fast Ethernet: Dawn of
a New Network", Prentice-Hall, Inc. (1996), pp. 158-175, the disclosures
of which are incorporated in their entirety by reference.
According to the current IEEE 802.3x Revision 1.0 Full-Duplex Draft,
stations 44 and the hub 46 are able to send a MAC control frame. Only one
MAC control frame is currently specified by IEEE 802.3x[2], namely the
PAUSE frame. The MAC control frame enables communications between the
respective MAC controllers 22, for example, handshaking, signaling, etc.
Hence, if station B detects an overload condition, described below, the
MAC 22 of the station B outputs a pause frame to the MAC 22 of station A,
requesting the station A to pause for a specified number of slot times.
Similarly, if the hub 46 detects an overload condition in its internal
buffers due to packet transmissions from one of the stations 44, the hub
can output a pause frame for a specified number of slot times to the one
station. A slot time (t.sub.s) is defined as 512 bit times for 10 MBit/s
and 100 MBit/s networks. The slot time (t.sub.s) has a preferred value of
4096 bit times for 1000 MBits/s networks, although other values may be
used consistent with network topology and propagation characteristics.
Each network element monitors its internal receive buffer to determine the
number of stored data bytes. For example, each network station 44 monitors
its internal MAC receive FIFO buffer 30b to determine the current number
of stored data bytes. If the number of stored data bytes exceeds a certain
threshold indicating that overflow of the receive FIFO buffer 30b will
soon occur, for example within 5-10 slot times (t.sub.s), the MAC pause
controller 38 of the corresponding network station instructs the MAC 22 to
initiate a flow control interval having a specified wait time (t.sub.w).
Each network station stores at least one threshold value and a time value
specifying the duration of the wait time (t.sub.w). The threshold levels
and the wait time (t.sub.w) may be programmed into a non-volatile memory
in the network interface 10, or may be remotely programmed by the hub 46,
a server, or a network administrator (i.e., some management entity).
FIG. 3 is a flow diagram illustrating a method of controlling transmission
of data packets. Each network station 10 independently executes the
disclosed method to prevent overflow of its corresponding MAC receive FIFO
buffer 30b. The method begins in step 52 by storing threshold data (L) and
wait time coefficients (k) in the wait time registers 40. The wait time
registers 40 shown in FIG. 7 may include a plurality of buffer thresholds
(L.sub.1 -L.sub.n) and respective wait time coefficients (k.sub.1
-k.sub.n). As described above with respect to FIG. 2, the buffer
thresholds (L.sub.i) and the respective wait time coefficients (k.sub.i)
may be received from a network manager via the media 50.
The MAC 22 then monitors the media 50 for activity, and detects the
presence of a data packet in step 54. The MAC 22 reads the header
information of the received data packet, and checks in step 56 if the
destination address of the received data packet matches the station
address. If the destination address does not match the station address,
the packet is discarded in step 58. If the destination address of the
received data packet matches the station address, the MAC 22 in step 60
recovers the payload data from the received data packet, and stores the
data bytes of the recovered payload data in the MAC receive FIFO buffer
30b and notifies the MAC pause controller 38 of the stored data bytes.
The MAC pause controller 38 then checks in step 62 to determine the status
of the MAC receive FIFO buffer 30b. The MAC pause controller 38 determines
in step 64 whether flow control is needed, described in detail below, and
initiates flow control by setting a flag (FC=1). If the MAC pause control
determines that the status of the MAC receive FIFO buffer 30b does not
require initiation of flow control, then the process returns to step 54
for reception of another data packet without interruption. However, if the
MAC pause controller 38 determines in step 64 that the status of the MAC
receive FIFO buffer 30b requires that flow control be initiated, the MAC
pause controller 38 instructs the MAC 22 in step 66 to execute flow
control for a determined wait time (t.sub.w) determined by the MAC pause
controller 38.
FIG. 4 is a flow diagram illustrating an exemplary implementation of flow
control in a full-duplex network In this implementation, the MAC 22
outputs a flow control signal corresponding to the wait time t.sub.w. As
shown on FIG. 4, after the wait time is determined in step 70, the MAC 22
sends a PAUSE frame including the determined wait time (t.sub.w). The
protocol for the PAUSE frame is further described in the working proposal
of IEEE 802.3x[2].
FIGS. 5A, 5B and 5C are flow diagrams illustrating in detail steps 62 and
64 of FIG. 3 determining the receive buffer status, determining whether
flow control is needed, and calculating an appropriate wait time (t.sub.w)
for the flow control mode. Although the disclosed arrangements provide
alternative techniques for initiating flow control, each of the variations
include the basic functions of determining whether flow control is
necessary, and selecting the wait time in response to the monitored number
of data bytes stored in the receive buffer.
As shown in FIG. 5A, the MAC pause controller 38 begins in step 86 by
determining the number of data bytes (N) stored in the MAC receive FIFO
buffer 30b. The MAC pause controller 38 then checks in step 88 whether the
number of stored data bytes (N) is greater than a minimum buffer threshold
(L.sub.1). If the number of stored data bytes (N) is not greater than the
minimum threshold (L.sub.1), then the MAC pause controller 38 determines
no flow control is necessary, sets an internal flow control flag to zero
(FC=0) in step 90, and returns to step 54 of FIG. 3.
If the MAC pause controller 38 determines in step 88 that the number of
stored data bytes (N) exceeds the minimum threshold (L.sub.1), the MAC
pause controller 38 checks in step 92 whether the station 10 is already in
a flow control mode by checking if the internal flag is already set. If
the internal flag (FC) is not set, the MAC pause controller 38 sets the
flag in step 94, and determines in step 96 the highest exceeded threshold
(L.sub.i).
FIG. 6A is a diagram illustrating the relative position of buffer
thresholds (L1, L2, . . . , L.sub.n) corresponding to predetermined levels
of data stored in the receive FIFO buffer 30b. As shown in FIG. 6A, if the
number of data bytes in the receive FIFO buffer 30b is greater than the
threshold L1, then a first wait time coefficient (k.sub.1) is selected
from wait time register 40. However, if the number of data bytes stored in
the receive FIFO buffer 30b exceeds the second threshold (L.sub.2), then
the MAC pause controller 38 selects the corresponding second wait time
coefficient (k.sub.2).
Hence, the MAC pause controller 38 determines in step 96 the highest exceed
threshold (L.sub.i) as shown on FIG. 6A, and accesses in step 98 the
corresponding coefficient (k.sub.i). The access wait time coefficient
(k.sub.i) is used to calculate the wait time as an integer multiple of
slot times (t.sub.s) in step 100. After calculating the wait time in step
100, the MAC pause controller 38 returns the calculated wait time
(t.sub.w) to the MAC 22 in step 66, which uses the determined wait time to
execute the flow control for full-duplex mode.
As shown in step 62 of FIG. 3 and more specifically in step 86 of FIG. 5A,
the MAC pause controller 38 repeatedly checks the number of stored data
bytes. For example, a transmitting station may continue to transmit data
packets to the receiving station after the receiving station has sent a
flow control message due to propagation delay between the two stations.
Hence, if in step 92 of FIG. 5A, the flow control flag is already set, the
MAC pause controller 38 determines in step 102 the highest exceeded
threshold (L.sub.j). The MAC pause controller 38 then checks in step 104
if the newly-exceeded second threshold (L.sub.j) is greater than the first
threshold (L.sub.i) in step 104. If the MAC pause controller 38 determines
that the number of stored data bytes (N) is greater than the first and
second thresholds (i.e., L.sub.j >L.sub.i), the MAC pause controller 38
accesses the corresponding wait time coefficient (k.sub.j) in step 106 and
recalculates the wait time (t.sub.w) in step 108. Hence, the method of
FIG. 5A enables the wait time (t.sub.w) defining the flow control interval
to be reset to a greater value, providing the MAC receive FIFO buffer 30b
additional time to empty the stored data bytes. Conversely, the MAC pause
controller 38 may reduce the wait time (t.sub.w) if the MAC receive FIFO
buffer 30b has had a sufficient number of data bytes removed.
Hence, FIGS. 5A and 6A illustrate a relatively simple arrangement where
flow control is initiated based upon predetermined threshold levels in the
MAC receive FIFO buffer 30b. If the number of data bytes continues to
exceed successive thresholds, the wait time can be adjusted accordingly to
provide additional time for the MAC receive FIFO buffer 30b to be emptied.
FIGS. 5B and 5C disclose alternative arrangements that monitor the removal
rate (r.sub.R) of data from the MAC receive FIFO buffer 30b. If the data
received by the network station exceeds the removal rate capacity of the
MAC receive FIFO buffer 30b, the MAC pause controller 38 initiates flow
control. The rate of emptying the receive buffers is determined by using
continuous monitoring sources or statistical counters.
FIG. 5B is a flow diagram illustrating one arrangement for determining when
to initiate flow control based upon the rate of emptying the receive
buffer 30b, also referred to as the removal rate (r.sub.R). The MAC pause
controller 38 begins in step 110 by calculating the data removal rate
(r.sub.R) in accordance with time stamp values recorded with respect to
respective thresholds. FIG. 6B illustrates the use of counters to
determine the data removal rate (r.sub.R). Specifically, the number of
stored data bytes (N) is monitored and a time stamp value (t.sub.a) is
recorded in a time stamp register 200a when the number of stored data
bytes reaches the first predetermined threshold (N=n.sub.1). A second time
stamp value (t.sub.b) is recorded in time stamp register 200b sometime
after the recording of the first time value in register 200a, i.e., when
the number of data bytes have been removed from the MAC receive FIFO
buffer 30b to a level corresponding to the second threshold (N=n.sub.2 | | |
