Multi-layer structures are electrochemically fabricated by depositing a first material, selectively etching the first material (e.g. via a mask), depositing a second material to fill in the voids created by the etching, and then planarizing the depositions so as to bound the layer being created and thereafter adding additional layers to previously formed layers. The first and second depositions may be of the blanket or selective type. The repetition of the formation process for forming successive layers may be repeated with or without variations (e.g. variations in: patterns; numbers or existence of or parameters associated with depositions, etchings, and or planarization operations; the order of operations, or the materials deposited). Other embodiments form multi-layer structures using operations that interlace material deposited in association with some layers with material deposited in association with other layers.

A plurality of semiconductor chips with the same structure are stacked to construct a multichip semiconductor device. In each of the semiconductor chips, an optional circuit is formed. In the optional circuit, fuses corresponding to the stacked-stage number of each chip are formed and the fuses are selectively cut off so as to permit each chip to individually receive a chip control signal.

The invention includes methods of fabrication and apparatuses. In at least some embodiments of the applicants' invention, the methods include processes of: maskless selective deposition of non-layered structures, selective etching and/or deposition without use of a separate mask and/or lithography techniques, retaining selected portions of sacrificial material during removal (e.g. etching) of other portions of sacrificial material, depositing materials other than the structural and sacrificial materials, including more than one type of structural and/or sacrificial material, and fabrication of interlacing elements. Embodiments of the methods of the invention provide increased capabilities, properties, flexibility and in the fabrication of three-dimensional structures by electro-deposition or other techniques. In certain embodiments, the apparatuses of the invention include structures having non-layered elements, retained sacrificial materials, three or more different deposited materials, and interlaced elements.

A method for forming a conductive via in a semiconductor component is disclosed. The method includes providing a substrate having a first surface and an opposing, second surface. At least one hole is formed in the substrate extending between the first surface and the opposing, second surface. A seed layer is formed on a sidewall defining the at least one hole of the substrate and coated with a conductive layer, and a conductive or nonconductive filler material is introduced into the remaining space within the at least one hole. A method of forming a conductive via through a substrate using a blind hole is also disclosed. Semiconductor components and electronic systems having substrates including the conductive via of the present invention are also disclosed.

A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. Additional layers of conductive materials may be used to provide a barrier layer and a noble metal cap for the conductive elements. The methods of the present invention may be used to fabricate an interposer for use in packaging semiconductor devices or a test substrate. Substrate precursor structures are also disclosed.