A scaleable bandwidth interconnect (SBI) for interconnection of physical layer devices with link layer devices which includes an ADD BUS interface operative to receive data from one of the link layer devices and direct it to one of the physical layer devices and a DROP BUS interface operative to receive data from one of the physical layer devices and direct it to one of the link layer devices. By utilizing buses to access each of the physical layer devices and the link layer devices permits interfacing between a high density of physical layer devices and a high density of link layer devices.

The interface circuit serves for connecting two apparatus by way of a bidirectional bus which comprises a data lead for transmitting data and a cycle lead for transmitting a cycle signal. The interface circuit consists of a circuit arrangement provided at each apparatus, which comprises a separating means for separating the data signal on the data lead and the cylce signal on the cycle lead in each case into a transmitting and a receiving branch, and which furthermore comprises in each case for the data lead and the cylce lead a bus driver having a differential transmitter and receiver. The data signals and cylce signals between the apparatus are transmitted via differential leads.

A serial bus controller having improved bus performance when a physical read request or a physical write request is present. A link and physical layer logic unit is provided, coupled to a serial bus having at least one peripheral device coupled thereto. A host interface is provided, coupled to a host data bus. A request FIFO is provided, coupled to receive a host memory read or write request packet from the link and physical layer logic unit, and coupled to said host interface. A physical read request FIFO is provided, coupled to receive a physical read request from the request FIFO for further processing of the physical read request. A physical write request FIFO is provided, coupled to receive a physical write response for transfer to the peripheral device.

An integrated circuit comprising a plurality of link layer controllers. The plurality of link layer controllers may be configured to operate independently in a first mode and cooperatively in a second mode.

Some of the circuits for executing processes on the physical layer are accommodated in a first chip that includes a link layer circuit. More specifically, an arbiter circuit composed only of a logic circuitry and having a relatively large circuit scale, and state machines, built in a control circuit, are accommodated in the first chip in the form of a control signal generation circuit. The other portions of the physical layer circuit remains in the second chip. A higher degree of integration of the first chip results in a higher degree of integration of many of the circuitry for executing processes on the physical layer.