Semiconductor integrated circuit having a DLL circuit and a special power supply circuit for the DLL circuit

What is claimed is:

1. A semiconductor integrated circuit having a plurality of elements including a DLL circuit, said DLL circuit receiving a first control signal and generating a second control signal synchronized with the first control signal by carrying out a phase synchronization process, said semiconductor integrated circuit comprising:

a power supply circuit keeping a power supply voltage at a specific voltage level and supplying the power supply voltage only to said DLL circuit,

wherein said DLL circuit comprises

a first delay circuit receiving the first control signal and supplying the second control signal having a specific delay to an object circuit;

a divider circuit receiving the first control signal;

a second delay circuit receiving a first output signal of said divider circuit;

a phase comparator having a first input to which a second output signal of said divider circuit is supplied, and a second input to which an output signal of said second delay circuit is supplied through a delay applying unit, said phase comparator carrying out a comparing process of comparing phases of the second output signal of said divider circuit and the output signal of said second delay circuit, said delay applying unit applying a delay corresponding to a time determined by transferring an output signal of said first delay circuit from said first delay circuit to said object circuit; and

a delay controller receiving an output signal of said phase comparator and controlling delay values of said first and second delay circuits.

2. A semiconductor integrated circuit as claimed in claim 1, wherein said power supply circuit is a voltage down generator.

3. A semiconductor integrated circuit as claimed in claim 2, wherein said voltage down generator comprises a transistor having a first electrode to which the power supply voltage of said semiconductor integrated circuit is applied, a control electrode to which a control voltage is applied, and a second electrode through which an output voltage of said voltage down generator is applied to said DLL circuit.

4. A semiconductor integrated circuit as claimed in claim 3, wherein said voltage down generator further comprises a capacitor for maintaining the control voltage applied to the gate of said transistor.

5. A semiconductor integrated circuit as claimed in claim 1, wherein said divider circuit generates the first and second output signals by X-dividing a frequency of the first control signal, and the comparing process of said phase comparator is carried out by every X periods of the first control signal, where X denotes an integer number of two or more.

6. A semiconductor integrated circuit as claimed in claim 5, wherein the first and second output signals of said divider circuit are complementary signals.

7. A semiconductor integrated circuit as claimed in claim 5, wherein said divider circuit generates the first signal where Y periods of the first control signal is at a first level and Z periods of the first control signal is at a second level, and the comparing process of said phase comparator is carried out at a timing of delaying Y periods of the first control signal, where Y denotes an integer number of two or more, and Z denotes an integer number.

8. A semiconductor integrated circuit as claimed in claim 5, wherein the first control signal is supplied through an input circuit, and the output signal of said second delay circuit is supplied to the second input of said phase comparator through a dummy line, a dummy object circuit, and a dummy input circuit.

9. A semiconductor integrated circuit as claimed in claim 8, wherein a sum of a delay of said input circuit, a minimum delay of said first delay circuit, a delay of said dummy line, and a delay of said object circuit exceeds one period of the first control signal, the comparing process of said phase comparator is carried out by a timing of delaying two or more periods of the first control signal.

10. A semiconductor integrated circuit as claimed in claim 1, wherein said semiconductor integrated circuit is a synchronous DRAM, and the object circuit is an output circuit of said synchronous DRAM.

11. A semiconductor integrated circuit comprising:

a DLL circuit receiving a first control signal and generating a second control signal synchronized with the first control signal by carrying out a phase synchronization process;

a first power supply circuit keeping a first power supply voltage at a specific voltage level and supplying the first power supply voltage to said DLL circuit;

peripheral circuits associated with said DLL circuit; and

a second power supply circuit supplying a second power supply voltage to said peripheral circuits,

wherein said DLL circuit comprises

a first delay circuit receiving the first control signal and supplying the second control signal having a specific delay to an object circuit,

a divider circuit receiving the first control signal,

a second delay circuit receiving a first output signal of said divider circuit,

a phase comparator having a first input to which a second output signal of said divider circuit is supplied, and a second input to which an output signal of said second delay circuit is supplied through a delay applying unit, said phase comparator carrying out a comparing process of comparing phases of the second output signal of said divider circuit and the output signal of said second delay circuit, said delay applying unit applying a delay corresponding to a time determined by transferring an output signal of said first delay circuit from said first delay circuit to said object circuit, and

a delay controller receiving an output signal of said phase comparator and controlling delay values of said first and second delay circuits.

12. A semiconductor integrated circuit as claimed in claim 11, wherein said first power supply circuit is a voltage down generator.

13. A semiconductor integrated circuit as claimed in claim 12, wherein said voltage down generator comprises a transistor having a first electrode to which the power supply voltage of said semiconductor integrated circuit is applied, a control electrode to which a control voltage is applied, and a second electrode through which an output voltage of said voltage down generator is applied to said DLL circuit.

14. A semiconductor integrated circuit as claimed in claim 13, wherein said voltage down generator further comprises a capacitor for maintaining the control voltage applied to the gate of said transistor.

15. A semiconductor integrated circuit as claimed in claim 11, wherein said divider circuit generates the first and second output signals by X-dividing a frequency of the first control signal, and the comparing process of said phase comparator is carried out by every X periods of the first control signal, where X denotes an integer number of two or more.

16. A semiconductor integrated circuit as claimed in claim 15, wherein the first and second output signals of said divider circuit are complementary signals.

17. A semiconductor integrated circuit as claimed in claim 15, wherein said divider circuit generates the first signal where Y periods of the first control signal is at a first level and Z periods of the first control signal is at a second level, and the comparing process of said phase comparator is carried out at a timing of delaying Y periods of the first control signal, where Y denotes an integer number of two or more, and Z denotes an integer number.

18. A semiconductor integrated circuit as claimed in claim 15, wherein the first control signal is supplied through an input circuit, and the output signal of said second delay circuit is supplied to the second input of said phase comparator through a dummy line, a dummy object circuit, and a dummy input circuit.

19. A semiconductor integrated circuit as claimed in claim 18, wherein a sum of a delay of said input circuit, a minimum delay of said first delay circuit, a delay of said dummy line, and a delay of said object circuit exceeds one period of the first control signal, the comparing process of said phase comparator is carried out by a timing of delaying two or more periods of the first control signal.

20. A semiconductor integrated circuit as claimed in claim 11, wherein said semiconductor integrated circuit is a synchronous DRAM, and the object circuit is an output circuit of said synchronous DRAM.

21. A semiconductor integrated circuit comprising:

a DLL circuit including

a first delay circuit receiving a first control signal and supplying a second control signal having a delay time to the first control signal,

a second delay circuit coupling to receive the first control signal,

a phase comparator having a first input, coupling to receive the first control signal, and a second input coupling to receive an output signal of said second delay circuit, said phase comparator comparing phases of the first control signal and the output signal of said second delay circuit, and

a delay controller receiving an output signal of said phase comparator and controlling delay values of said first and second delay circuits; and

a power supply circuit keeping a power supply voltage at a specific voltage level and supplying the power supply voltage exclusively to said DLL circuit.

22. A semiconductor integrated circuit comprising:

an input buffer circuit receiving an external control signal to supply a first control signal;

a DLL circuit receiving the first control signal and generating a second control signal synchronized with the first control signal;

a first power supply circuit keeping a first power supply voltage at a specific voltage level and supplying the first power supply voltage exclusively to said DLL circuit; and

a second power supply circuit supplying a second power supply voltage to said input buffer circuit,

wherein said DLL circuit comprises

a first delay circuit receiving the first control signal and supplying the second control signal having a delay time to the first control signal,

a second delay circuit coupling to receive the first control signal,

a phase comparator having a first input, coupling to receive the first control signal, and a second input, coupling to receive an output signal of said second delay circuit, said phase comparator comparing phases of the first control signal and the output signal of said second delay circuit, and

a delay controller receiving a output signal of said phase comparator and controlling delay values of said first and second delay circuits.

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a DLL (Delay Locked Loop) circuit and a special power supply circuit for the DLL circuit.

2. Description of the Related Art

Recently, an operation speed of a semiconductor integrated circuit has been increased, and a circuit scale thereof has become large. Further, it has been necessary to supply a synchronized signal (phase synchronized clock signal) to a specific circuit in a large scale semiconductor integrated circuit.

For example, an operation speed of a memory device, e.g., a synchronous DRAM (SDRAM), now exceeds 100 MHz, and a DLL circuit must be used to synchronize a signal with an external clock and supply the synchronized signal to a plurality of output buffers, so as to remove a delay of an internal clock. Namely, a phase of the external clock is coincident with that of the internal clock, and thereby a delay or fluctuation of an access time is removed.

Specifically, in a SDRAM, a DLL circuit must be used to synchronize an internal clock with an external clock and supply the synchronized internal clock to a plurality of output buffers, so as to remove a delay of an internal clock. Namely, a phase of the external clock is coincident with that of the internal clock, and thereby a delay or fluctuation of an access time is removed. Further, in accordance with increasing the operation speed of the semiconductor integrated circuit, the internal clock generated by the DLL circuit should have much higher accuracy.

In a semiconductor integrated circuit of a related art, a DLL circuit and peripheral circuits except for the DLL circuit commonly receive the same power supply voltage output from a power supply circuit. Therefore, when the peripheral circuits use a large current from the power supply circuit or when noise is caused in the power supply voltage in an area of the peripheral circuits, the power supply voltage applied to the DLL circuit is lowered or fluctuated by the noise, and the internal clock output from the DLL circuit is not stable and the accuracy (synchronization with the external clock) of the internal clock is decreased. In addition, the internal clock output from the DLL circuit may include a jitter.

The related arts and their associated problems will be described in detail later with reference to the accompanying drawings.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor integrated circuit having a DLL circuit which can generate an internal clock being stable and accurately synchronized with an external clock without including a jitter.

According to the present invention, there is provided a semiconductor integrated circuit having a DLL circuit for receiving a first control signal and generating a second control signal synchronized with the first control signal by carrying out a phase synchronization process, comprising a power supply circuit for supplying a power supply voltage only to the DLL circuit.

Further, according to the present invention, there is provided a semiconductor integrated circuit comprising a DLL circuit for receiving a first control signal and generating a second control signal synchronized with the first control signal by carrying out a phase synchronization process; a first power supply circuit for supplying a power supply voltage to the DLL circuit; peripheral circuits except for the DLL circuit; and a second power supply circuit for supplying a power supply voltage to the peripheral circuits.

The first power supply circuit may be a voltage down generator. The voltage down generator may comprise a transistor having a source to which a power supply voltage of the semiconductor integrated circuit is applied, a gate to which a control voltage is applied, and a drain through which an output voltage of the voltage down generator is applied to the DLL circuit. The voltage down generator may further comprise a capacitor for maintaining the control voltage applied to the gate of the transistor.

The DLL circuit may comprise a first delay circuit for receiving the first control signal and supplying the second control signal having a specific delay to an object circuit; a divider circuit for receiving the first control signal; a second delay circuit for receiving a first output signal of the divider circuit; a phase comparator having a first input to which a second output signal of the divider circuit is supplied and a second input to which an output signal of the second delay circuit is supplied through a delay applying unit, for carrying out a comparing process of comparing the phases of the second output signal of the divider circuit and the output signal of the second delay circuit, the delay applying unit applying a delay corresponding to a time determined by transferring an output signal of the first delay circuit from the first delay circuit to the object circuit; and a delay controller for receiving an output signal of the phase comparator and controlling delay values of the first and second delay circuits.

The divider circuit may generate the first and second output signals by X-dividing a frequency of the first control signal, and the comparing process of the phase comparator may be carried out by every X periods of the first control signal, where X denotes an integer number of two or more. The first and second output signals of the divider circuit may be complementary signals. The divider circuit may generate the first signal where Y periods of the first control signal is at a first level and Z periods of the first control signal is at a second level, and the comparing process of the phase comparator may be carried out at a timing of delaying Y periods of the first control signal, where Y denotes an integer number of two or more, and Z denotes an integer number.

The first control signal may be supplied through an input circuit, and the output signal of the second delay circuit may be supplied to the second input of the phase comparator through the dummy line, a dummy object circuit, and a dummy input circuit. A sum of a delay of the input circuit, a minimum delay of the first delay circuit, a delay of the dummy line, and a delay of the object circuit may exceed one period of the first control signal, the comparing process of the phase comparator may be carried out by a timing of delaying two or more periods of the first control signal. The semiconductor integrated circuit may be a synchronous DRAM, and the object circuit may be an output circuit of the synchronous DRAM.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from the description of the preferred embodiments as set forth below with reference to the accompanying drawings, wherein:

FIG. 1 is a block diagram showing an example of a semiconductor integrated circuit according to the related art;

FIG. 2 is a block diagram showing an embodiment of a semiconductor integrated circuit according to the present invention;

FIG. 3 is a diagram showing a main portion of the semiconductor integrated circuit of FIG. 2;

FIG. 4 is a diagram showing an example of a divider circuit provided in the semiconductor integrated circuit of FIG. 2;

FIG. 5 is a diagram showing waveforms of nodes in the divider circuit of FIG. 4;

FIG. 6 is a timing chart showing an operation of the semiconductor integrated circuit employing the divider circuit of FIG. 4;

FIGS. 7A, 7B, and 7C are diagrams showing an example of a delay circuit of a semiconductor integrated circuit according to the present invention;

FIG. 8 is a circuit diagram showing an example of a delay control circuit of a semiconductor integrated circuit according to the present invention;

FIG. 9 is a timing chart showing an operation of the delay control circuit of FIG. 8;

FIG. 10 is a circuit diagram showing an example of a phase comparator (phase comparing section) of a semiconductor integrated circuit according to the present invention;

FIGS. 11A, 11B, and 11C are timing charts showing operations of the phase comparator of FIG. 10;

FIG. 12 is a circuit diagram showing an example of a phase comparator (amplifying section) of a semiconductor integrated circuit according to the present invention;

FIG. 13 is a timing chart showing an operation of a JK flip-flop of the amplifying section of FIG. 12;

FIG. 14 is a timing chart showing an incremental operation of the amplifying section of FIG. 12;

FIG. 15 is a timing chart showing a sustain operation of the amplifying section of FIG. 12;

FIG. 16 is a timing chart showing a decremental operation of the amplifying section of FIG. 12;

FIG. 17 is a block diagram showing a synchronous DRAM according to the present invention;

FIG. 18 is a timing chart showing an operation of the synchronous DRAM of FIG. 17;

FIG. 19 is a block diagram showing essential parts of the synchronous DRAM of FIG. 17;

FIG. 20 is a circuit diagram showing an example of a data output buffer of a semiconductor integrated circuit according to the present invention; and

FIG. 21 is a diagram showing an example of a dummy line for transmitting a dummy internal clock signal in a semiconductor integrated circuit according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

For a better understanding of the preferred embodiments of the present invention, a related art and the problem thereof will be explained.

FIG. 1 shows an example of a semiconductor integrated circuit according to the related art. In FIG. 1, reference numeral 1 denotes a clock input pad, 21 denotes an input circuit (clock buffer), 22 denotes a dummy input circuit (clock buffer), and 3 denotes a DLL circuit. Further, reference numeral 41 denotes a clock signal line (real line), 42 denotes a dummy line, 51 denotes an output circuit (output buffer), 52 denotes a dummy output circuit (output buffer), 6 denotes a data output pad, 7 denotes a dummy load capacitor, 90 denotes a power supply circuit.

As shown in FIG. 1, the DLL circuit 3 comprises a phase comparator (digital phase comparator) 31, a delay controller 32, a delay circuit 33, and a dummy delay circuit 34. An external clock (external input clock signal) CLK is supplied to the phase comparator 31 through the input circuit 2 (with reference to a signal S1), and the external clock CLK is also supplied to the phase comparator 31 through the dummy delay circuit 34, dummy line 42, dummy output circuit 52, and dummy input circuit 22 (with reference to a signal S0). These signals S1 and S0 are compared (phase-compared) by the phase comparator 31, and the delay controller 32 is controlled by output signals of the phase comparator 31. Note that the signal S0 supplied to the phase comparator 31 from the dummy input circuit 22 is a signal of delaying one clock cycle of the external clock CLK by the dummy line 42, and the like. The delayed signal S0 is compared with the signal S1 output from the input circuit 21 by the phase comparator 31.

The delay controller 32 controls the delay circuit 33 and the dummy delay circuit 34 to apply the same delay (delay value) in accordance with output signals (comparison result) of the phase comparator 31. Therefore, the delay (delay time) caused by the input circuit 21, delay circuit 33, real line 41, and output circuit 51 are removed, and the internal clock signal for the output circuit 51 is supplied at the same timing of inputting the external clock CLK.

In the semiconductor integrated circuit of FIG. 1, the input circuit 21, dummy input circuit 22, output circuit 51, dummy output circuit 52, and DLL circuit 3 receive a voltage output from the power supply circuit 90. Namely, in the semiconductor integrated circuit according to the related art shown in FIG. 1, an output voltage of the power supply circuit 90 is commonly supplied to the DLL circuit 3 (phase comparator 31, delay controller 32, delay circuit 33, and dummy delay circuit 34) and peripheral circuits except for the DLL circuit 3 (input circuit 21, dummy input circuit 22, output circuit 51, dummy output circuit 52, and the like). Note that the peripheral circuits include command decoder (102), address buffer/register and bank selector (103), mode register (106), and the like, as shown in FIG. 17. Further, the Dll circuit 3 is used to generate the internal clock with high accuracy.

As described above, in the semiconductor integrated circuit of the related art shown in FIG. 1, the DLL circuit 3 (31, 32, 33, 34) and the peripheral circuits (21, 22, 51, 52, and the like) commonly receive the same power supply voltage output from the power supply circuit 90. Therefore, when the peripheral circuits use a large power (large current) of the power supply circuit 90 or when noise is caused in the power supply voltage in an area of the peripheral circuits, the power supply voltage applied to the DLL circuit 3 is lowered or fluctuated by the noise, and the delay caused by the delay circuit 33 (34) is changed (fluctuated), so that the phase comparison operation of the phase comparator 31 should be frequently carried out. Namely, the internal clock output from the DLL circuit 3 is not stable and the accuracy (synchronization with the external clock) of the internal clock becomes decreased. In addition, the internal clock output from the DLL circuit 3 may include jitter.

Below, preferred embodiments of a semiconductor integrated circuit according to the present invention will be described with reference to the accompanying drawings.

FIG. 2 shows an embodiment of a semiconductor integrated circuit according to the present invention. In FIG. 2, reference numeral 1 denotes a clock input pad, 21 denotes an input circuit (clock buffer), 22 denotes a dummy input circuit (clock buffer), and 3 denotes a DLL circuit. Further, reference numeral 41 denotes a clock signal line (real line), 42 denotes a dummy line, 51 denotes an output circuit (output buffer: object circuit), 52 denotes a dummy output circuit (output buffer), 6 denotes a data output pad, 7 denotes a dummy load capacitor, 91 denotes a first power supply circuit (first voltage down generator), and 92 denotes a second power supply circuit (second voltage down generator).

As shown in FIG. 2, the DLL circuit 3 comprises a divider (frequency divider) circuit 30, a phase comparator (digital phase comparator) 31, a delay controller 32, a delay circuit 33, and a dummy delay circuit 34. The divider circuit 30 receives an external clock CLK (signal S1: first control signal) through the input circuit 21, and a frequency of the external clock CLK is divided by the divider circuit 30 and output. Namely the divider circuit 30 supplies a first output signal (signal S2) to the dummy delay circuit 34, and also supplies a second output signal (signal S3) to a first input of the phase comparator 31. Note that the first output signal (S2) of the divider circuit 30 is supplied to a second input (signal S0) of the phase comparator 31 through the dummy delay circuit 34, dummy line 42, dummy output circuit 52, and dummy input circuit 22, and the phase comparator 31 controls the delay controller 32 by carrying out the phase comparison between the signals S3 and S0. The output signal (second control signal: internal clock) of the delay circuit 33 is supplied to the output circuit (object circuit) 51 through the real line 41 as an output signal of the DLL circuit 3.

The delay controller 32 controls the delay circuit 33 and the dummy delay circuit 34 to apply the same delay (delay value) in accordance with output signals (comparison result) of the phase comparator 31. Therefore, the delay (delay time) caused by the input circuit 21, delay circuit 33, real line 41, and output circuit 51 are removed, and the internal clock signal for the output circuit 51 is supplied at the same timing of inputting the external clock CLK.

By the way, when one period (clock cycle) of the external clock CLK is shorter than the total delay of the input circuit 21, output circuit 51, real line (signal line) 41, and the like, a synchronous internal clock cannot be generated by synchronizing with one clock cycle preceding timing of the external clock CLK by using the DLL circuit 3. Therefore, in this embodiment, when the one clock cycle (one period) of the external clock CLK is shorter than the delay of the signal line, and the like, the internal clock is generated by synchronizing with the two clock cycle preceding timing of the external clock CLK. Namely, the phase comparator 31 carries out the phase comparison operation (phase comparison process) at the timing of two clock cycle delayed timing of the external clock CLK.

In this embodiment, a rising edge of the internal clock output from the DLL circuit 3 and a rising edge of the two-clock-cycle delayed external clock input to the DLL circuit 3 are synchronized (locked) by the phase comparator 31 (phase comparison operation). Namely, in the present embodiment, as shown in FIG. 2, a divider circuit 30 for receiving an output signal of the input circuit 21 is provided, a first output signal S2 of the divider circuit 30 is supplied to the dummy delay circuit 34, and a second output signal S3 of the divider circuit 30 is supplied to a first input of the phase comparator 31.

FIG. 3 shows a main portion of the semiconductor integrated circuit of FIG. 2.

As shown in FIGS. 2 and 3, in the semiconductor integrated circuit of the present embodiment, two power supply circuits 91 and 92 are provided. Namely, a first power supply circuit (first voltage down generator) 91 is a special power supply circuit only for the DLL circuit 3, and thus an output voltage of the first power supply circuit 91 is applied to the divider circuit 30, phase comparator 31, delay controller 32, delay circuit 33, and dummy delay circuit 34 constituting the DLL circuit 3.

As shown in FIGS. 2 and 3, a second power supply circuit (second voltage down generator) 92 is provided for the circuits (peripheral circuits) except for the DLl circuit 3. Namely, in the semiconductor integrated circuit of FIG. 2, an output voltage of the second power supply circuit 92 is applied to the input circuit 21, dummy input circuit 22, output circuit 5