 |
Claims  |
|
|
What is claimed is:
1. A method of determining the non-linearity and non-ideality of an
analog-to-digital device under test, the device under test having at least
one integrator, a respective non-linear integrator model, and
non-linearity parameters, said method comprising the following steps:
generating a model data set from a plurality of simulations of the
analog-to-digital device under test employing the respective non-linear
integrator model wherein the respective non-linear integrator model
comprises at least one polynomial equation;
generating an n-dimensional prediction equation corresponding to said model
data set;
measuring the input response of each respective non-linear integrator to
generate a respective input response test data set;
generating a plurality of numerical values for the non-linearity
coefficients in the non-linear integrator model from said respective test
data set; and
determining the acceptability of the analog-to-digital device under test by
solving said prediction equation using said plurality of numerical values
as input values.
2. The method as recited in claim 1, wherein said step of determining the
acceptability of the analog-to-digital device under test further comprises
the step of selecting a respective region of a sufficiency surface
corresponding to an acceptable signal-to-noise ratio (SNR) limit and
corresponding to an acceptable signal-to-distortion ratio (SDR) limit of
each respective integrator.
3. The method as recited in claim 1, wherein said step of generating a
plurality of numerical values comprises the step of generating a
respective set of polynomial coefficients corresponding with said
respective input response test data set.
4. The method as recited in claim 3, wherein said step of generating a
plurality of numerical values further comprises the step of using a
Chebychev n-dimensional prediction function to generate a respective set
of polynomial coefficients corresponding to said plurality of numerical
values.
5. The method as recited in claim 1, wherein said step of generating a
model data set comprises the step of using a Gibbs Data Sampling method.
6. The method as recited in claim 2, wherein said step of generating a
model data set comprises the step of using a Linear Search Sampling
method.
7. The method as recited in claim 6, further comprises the step of
generating said model data set within a tolerance shell around said SNR
and said SDR.
8. The method as recited in claim 2, wherein said step of generating a
model data set comprises the step of using an Improved Linear Search
Sampling method.
9. The method as recited in claim 8, wherein said step of using an Improved
Linear Search Sampling method further comprises the step of generating
said model data set within a tolerance shell around said SNR and said SDR.
10. The method as recited in claim 4, wherein said step of generating said
plurality of numerical values further comprises the step of selecting a
sub set of said n-dimensional polynomial coefficients having "M" terms,
wherein said "M" terms correspond to coefficients having the greatest
influence on the respective polynomial.
11. The method as recited in claim 1, wherein said step of generating a
model data set employing the non-linear integrator model further comprises
the step of using at least one model capacitor having input non-linearity.
12. The method as recited in claim 11, wherein said respective capacitor
model is a switched capacitor model.
13. The method as recited in claim 1, wherein said step of generating a
model data set employing the non-linear integrator model further comprises
the step of using at least one model capacitor having integration
non-linearity.
14. The method as recited in claim 13, wherein said respective capacitor
model is a switched capacitor model.
15. The method as recited in claim 1, wherein said step of generating an
n-dimensional prediction equation comprises the step of using a genetic
algorithm to generate said prediction equation.
16. A method of designing an analog-to-digital device by determining the
non-linearity and non-ideality of the design, the design having at least
one integrator design model, a respective non-linear integrator design
model, and non-linearity coefficients, said method comprising the
following steps:
generating a model data set from a plurality of simulations of the
analog-to-digital design employing the respective non-linear integrator
design model wherein the non-linear design model comprises at least one
polynomial equation;
generating an n-dimensional prediction equation corresponding to said model
data set;
measuring the input response of each respective non-linear integrator
design model to generate a respective input response test data set;
generating a plurality of numerical values for the non-linearity
coefficients in the respective non-linear design model from said
respective test data set; and
determining the acceptability of the analog-to-digital design by solving
said prediction equation using said plurality of numerical values as input
values.
17. The method as recited in claim 16, wherein said step of determining the
acceptability of the design further comprises the step of selecting a
respective region of a sufficiency surface corresponding to an acceptable
signal-to-noise ratio (SNR) limit and corresponding to an acceptable
signal-to-distortion ratio (SDR) limit of each respective non-linear
integrator design model.
18. The method as recited in claim 16, wherein said step of generating an
n-dimensional prediction equation comprises the step of using a genetic
algorithm to generate said prediction equation.
19. The method as recited in claim 16, wherein said step of generating a
plurality of numerical values comprises the step of generating a
respective set of polynomial coefficients corresponding with said
respective input response test data set.
20. The method as recited in claim 19, wherein said step of generating a
plurality of numerical values further comprises the step of using a
Chebychev n-dimensional prediction function to generate a respective set
of polynomial coefficients corresponding to said plurality of numerical
values.
21. The method as recited in claim 16, wherein said step of generating a
model data set comprises the step of using a Gibbs Data Sampling method.
22. The method as recited in claim 17, wherein said step of generating a
model data set comprises the step of using a Linear Search Sampling
method.
23. The method as recited in claim 22, further comprises the step of
generating said model data set within a tolerance shell around said SNR
and said SDR.
24. The method as recited in claim 17, wherein said step of generating a
model data set comprises the step of using an Improved Linear Search
Sampling method.
25. The method as recited in claim 24, wherein said step of using an
Improved Linear Search Sampling method further comprises the step of
generating said model data set within a tolerance shell around said SNR
and said SDR.
26. The method as recited in claim 20, wherein said step of generating said
plurality of numerical values further comprises the step of selecting a
sub set of said n-dimensional polynomial coefficients having "M" terms,
wherein said "M" terms correspond to coefficients having the greatest
influence on the respective polynomial.
27. The method as recited in claim 16, wherein said step of generating a
model data set employing the non-linear integrator design model further
comprises the step of using at least one model capacitor having input
non-linearity.
28. The method as recited in claim 27, wherein said respective capacitor
model is a switched capacitor model.
29. The method as recited in claim 16, wherein said step of generating a
model data set employing the non-linear integrator design model further
comprises the step of using at least one model capacitor having
integration non-linearity.
30. The method as recited in claim 29, wherein said respective capacitor
model is a switched capacitor model.
31. An apparatus for determining the non-linearity and non-ideality of an
analog-to-digital device under test, the device under test having at least
one integrator, a respective non-linear integrator model, and
non-linearity parameters, said apparatus comprising:
means for generating a model data set from a plurality of simulations of
the analog-to-digital device under test employing the respective
non-linear integrator model wherein the non-linear integrator model
comprises at least one polynomial equation;
means for generating an n-dimensional prediction equation corresponding to
said model data set;
means for measuring the input response of each respective non-linear
integrator to generate a respective input response test data set;
means for generating a plurality of numerical values for the non-linearity
coefficients in the non-linear integrator model from said respective test
data set; and
means for determining the acceptability of the analog-to-digital device
under test by solving said prediction equation using said plurality of
numerical values as input values.
32. The apparatus as recited in claim 31, wherein said means for
determining the acceptability of the analog-to-digital device under test
further comprises means for selecting a respective region of a sufficiency
surface corresponding to an acceptable signal-to-noise ratio (SNR) limit
and corresponding to an acceptable signal-to-distortion ratio (SDR) limit
of each respective integrator.
33. The apparatus as recited in claim 31, wherein said means for generating
a plurality of numerical values comprises means for generating a
respective set of polynomial coefficients corresponding with said
respective input response test data set.
34. The apparatus as recited in claim 33, wherein said means for generating
a plurality of numerical values further comprises means for using a
Chebychev n-dimensional prediction function to generate a respective set
of polynomial coefficients corresponding to said plurality of numerical
values.
35. The apparatus as recited in claim 31, wherein said means for generating
a model data set comprises means for using a Gibbs Data Sampling method.
36. The apparatus as recited in claim 32, wherein said means for generating
a model data set comprises means for using a Linear Search Sampling
method.
37. The apparatus as recited in claim 36, further comprises means for
generating said model data set within a tolerance shell around said SNR
and said SDR.
38. The apparatus as recited in claim 32, wherein said means for generating
a model data set comprises means for using an Improved Linear Search
Sampling method.
39. The apparatus as recited in claim 38, wherein said means for using an
Improved Linear Search Sampling method further comprises means for
generating said model data set within a tolerance shell around said SNR
and said SDR.
40. The apparatus as recited in claim 34, wherein said means for generating
said plurality of numerical values further comprises means for selecting a
sub set of said n-dimensional polynomial coefficients having "M" terms,
wherein said "M" terms correspond to coefficients having the greatest
influence on the respective polynomial.
41. The apparatus as recited in claim 31, wherein said means for generating
a model data set employing the non-linear integrator model further
comprises means for using at least one model capacitor having input
non-linearity.
42. The apparatus as recited in claim 41, wherein said respective capacitor
model is a switched capacitor model.
43. The apparatus as recited in claim 31, wherein said means for generating
a model data set employing the non-linear integrator model further
comprises means for using at least one model capacitor having integration
non-linearity.
44. The apparatus as recited in claim 43, wherein said respective capacitor
model is a switched capacitor model.
45. The apparatus as recited in claim 31, wherein said means for generating
an n-dimensional prediction equation comprises the step of using a genetic
algorithm to generate said prediction equation. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
BACKGROUND OF THE INVENTION
This invention relates to the testing and design of integrator based
analog-to-digital converter circuits, and more particularly to a method of
designing and testing a sigma-delta based analog-to-digital converter
circuit using optimized polynomial representations of the non-linearity of
the transfer function of the circuit to predict the signal-to-noise ratio
(SNR) and the signal-to-distortion ratio (SDR).
The timely design of integrated circuits for economical and reliable
insertion into products and systems requires design methodologies which
increase the likelihood of obtaining the required performance with little
or no design iteration. Operation is required at the designed level of
performance over manufacturing tolerances, and over expected environmental
and operational conditions. Computer aided design (CAD) methods are used
extensively in integrated circuit (IC) design to increase the robustness
to variations in manufacturing tolerances as well as environmental and
operational conditions. Enhanced CAD tools that enable rapid and
verifiable product designs are a critical need to maintain the pace of
productivity enhancement in IC development.
Semiconductor manufacturing processes have inherent limitations in the
tolerances that can be maintained on key parameters important for analog
and digital integrated circuit design. Limitations in lithography cause
uncertainty in device geometry such as metal-oxide semiconductor (MOS)
transistor length and width which determine amplifier gain-bandwidth and
logic drive strength. Variability in oxide growth rate contributes to
variable oxide thickness which in turn causes variability in transistor
capacitance and transconductance. Uncertainties in doping profiles on
implants and diffusions cause variance in resistor values as well as
transistor parasitic capacitance. The circuit impact of these
manufacturing tolerances must be considered when designing integrated
circuits.
Once in a product or system, an integrated circuit must maintain the
required level of performance over all expected conditions including
temperature excursions, variations in power supply voltage, and
fluctuations in input signal integrity. Since test of each chip produced
over all expected environmental or operational condition is impractical,
consideration of variations is critical in design of robust, reliable
integrated circuits. To design an integrated circuit for robustness with
respect to the always present variations, requires simulation of the
circuit over the ranges of these variations. This task is reasonable for
circuits such as op-amps, comparators, switches, and logic gates whose
performance can be evaluated in direct time-domain simulations taking
seconds, minutes, or hours. When the simulations require days or more to
run on the fastest engineering workstations, the design cycle becomes too
long to practically meet the market demands for the technology. In
situations where direct circuit simulations are impractical, other CAD
methods must be employed.
Design of complex, mixed analog-digital integrated circuits poses
challenges to designers, and places strong demands on CAD tools. Circuits
such as analog-to-digital converters (ADCs), digital-to-analog converters
(DACs), and phase-lock loops (PLLs) are examples of circuits which
challenge direct time-domain simulation. The common feature of these
circuits is that the circuits resist linearization since they operate in
several different linear and non-linear regimes. The result is complex
transient behavior which requires time-domain simulation with a fine
time-step.
With the advent of the introduction of computers into most products and
systems, the need for circuits to interface between our analog world and
the digital world of the computer has increased dramatically. The growing
need for high performance, low power, and low cost electronic systems has
resulted in the invention of many elegant ADC circuits. As the resolution
increases, more power is required to increase the sample rate. The
decreasing efficiency with resolution is related to difficulties
associated with component matching and absolute voltage and current
accuracy required, which are limited by semiconductor process technology
and power supply levels. When resolutions increase, circuit complexity
increases to compensate for the limitations in component matching and
accuracy limits. The circuit complexity increases the power consumption
accordingly.
The low resolution ADCs are typically pipelined or folded flash
architectures. The high resolution converters are typically dual-slope,
successive approximation, or sigma-delta architectures. The sigma-delta
architecture is capable of attaining high resolution analog-to-digital
conversion with moderate sample rates and low power consumption in a CMOS
process, and this makes it attractive for integration into mixed
analog-digital circuits. The sigma-delta modulator uses oversampling of
the input signal combined with low resolution quantization and digital
filtering to accomplish analog-to-digital conversion. The oversampling of
the low bandwidth signal poses a particularly difficult problem in circuit
simulation of sigma-deltas. High accuracy analog simulations need to be
run for many sample periods to evaluate the result of conversion after
digital filtering. Simulations in a circuit simulator, such as SPICE.TM.,
may take days for a single case, with the simulated performance perhaps
limited to less than 15 bits due to rounding and truncation errors which
accumulate over the large number, possibly millions, of time steps
required for accurate simulation.
Several CAD methods for the simulation of sigma-delta modulators have been
developed. The existing methods are useful in determining the performance
of subcircuits required to achieve a desired level of performance, or to
verify the performance once all the subcircuits have been designed.
However, a methodology which is useful in optimizing the subcircuit
designs is clearly lacking. A methodology which can quickly and easily
estimate the sigma-delta performance given simulation data of the
subcircuits could be used in the automated optimization of the subcircuits
and lead to shorter design cycles and more robust designs. As such, a
sigma-delta method is desired which does not rely on simulation of the
sigma-delta loop in order to evaluate the SNR and SDR of a modulator
instance.
Simulation and testing of over-sampled analog-to-digital converters (ADCs)
requires the simulation or acquisition of thousands of consecutive samples
in order to determine resolution and linearity. Typically the ADC is run
for 16K to 64K clock cycles and an Fast Fourier Transform (FFT) performed
on pre-decimated or post-decimated samples. The signal-to-noise ratio
(SNR) and signal-to-distortion ratio (SDR) are computed from the FFT
spectrum. The long time-domain modulator simulations consume significant
design time. Testing a multi-channel ADC over several operational
conditions using this method adds substantial cost to the integrated
circuit. As such, it is desirable to reduce the test time so as to improve
design optimization.
BRIEF DESCRIPTION OF THE INVENTION
The present invention provides a method and apparatus which uses data
containing non-linearity information regarding integrator circuits in
over-sampled Analog-to-Digital Converters (ADCs) to predict the
Signal-to-Distortion Ratio (SDR) and Signal-to-Noise Ratio (SNR). The
present invention determines the non-linearity and non-ideology of an
analog-to-digital device under test, the device under test having at least
one integrator, a respective non-linear integrator model, and
non-linearity parameters. The present invention includes the following
steps: generating a model data set from a plurality of simulations of the
analog-to-digital device under test employing the respective non-linear
integrator model; generating an n-dimensional prediction equation
corresponding to the model data set; measuring the input response of each
respective non-linear integrator to generate a respective input response
test data set; generating a plurality of numerical values for the
non-linearity coefficients in the non-linear integrator model from the
respective test data set; and determining the acceptability of the SDR and
SNR by solving the prediction equation using the plurality of numerical
values as input data to the prediction equation.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the testing method for the design process of
the present invention;
FIG. 2 is a block diagram of the in situ testing process of the present
invention;
FIG. 3 is a schematic block diagram of a second order, first order cascade
(SOFOC2), third order sigma-delta modulator;
FIG. 4 is a schematic block diagram of a second order, first order cascade
(SOFOC2), third order sigma-delta modulator with linearized quantizers;
FIG. 5 is a flow diagram of a genetic algorithm used in the present
invention;
FIG. 6 is a block diagram of a non-linear integrator model used in the
present invention;
FIG. 7 is a two dimensional plot of a SNR for non-linearities for a.sub.17
and a.sub.25 using 512 points in base-band;
FIG. 8 is a two dimensional plot of a SNR for non-linearities for a.sub.17
and a.sub.25 using 8192 points in base-band;
FIG. 9 is a plot of the simulated and predicted SNR using Linear Search
Sampling;
FIG. 10 is a plot of the simulated and predicted SNR using Improved Linear
Search Sampling;
FIG. 11 is a plot of the simulated and predicted SNR using Gibbs Data
Sampling;
FIG. 12 is a schematic diagram of three integrators of the present
invention;
FIG. 13 is a schematic diagram of a fully differential comparator used in
the SOFOC2 circuit illustrated in FIG. 4;
FIG. 14 is a plot of the simulated SDR and SNR for the SOFOC2 circuit
illustrated in FIG. 4;
FIG. 15 is a flow diagram of the interactive sigma-delta optimization
procedure using a look-up table simulation methodology; and
FIG. 16 is a flow diagram for determining the SNR and SDR of the present
invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring now to the drawings, wherein like numerals represent like
elements throughout. The present invention, depicted in the flow diagram
50 in FIG. 16, is described most broadly in the following five steps:
S1. Generate a model data set based on a plurality of simulations of the
analog-to-digital device under test.
S2. Generate a prediction equation from the model data
S3. Measure, in parallel, the input and output of each integrator in the
analog-to-digital device to generate a input response test data set. The
measurements may also be made serially.
S4. Use the input response test data set gathered to determine the
non-linearity coefficients which define the non-linearity and
non-idealities for the functions f.sub.1 and f.sub.2, where f.sub.1 is
representative of the sampling non-linearity function and f.sub.2 is
representative of the integration distorting function.
S5. Use the calculated non-linearity and non-ideality to predict the
performance characteristic of the analog-to-digital device, as defined by
the signal-to-noise ratio and the signal-to-distortion ratio.
In one embodiment, these steps may be used to evaluate the acceptability of
the device as an analog-to-digital device under test. In another
embodiment, these steps may be used to evaluate the analog-to-digital
device, as a simulation of an integrator based analog-to-digital design,
so as to optimize the performance of the analog-to-digital design.
The functions f.sub.1 and f.sub.2 are developed from simulations of the
integrator portion of the device. Function f.sub.1 is related the input
voltage (.nu..sub.in) to the device as illustrated in equation (1),
.function..sub.1 (.nu..sub.in)=.alpha..sub.0.nu..sub.in
+.alpha..sub.1.nu..sub.in.sup.2 +.alpha..sub.2.nu..sub.in.sup.3 + . . .
(1)
where .alpha..sub.n are "n" constants chosen to produce the best curve fit,
and "n" is a number equal to the total number of constants identified and
equal to the number of integrators in the device.
Function f.sub.2 is related to the input voltage (.nu..sub.in) to the
device as illustrated in equation (2),
.function..sub.2 (.nu..sub.in)=.beta..sub.0 (.nu..sub.in
-.nu..sub.ref)+.beta..sub.1 (.nu..sub.in -.nu..sub.ref).sup.2
+.beta..sub.2 (.nu..sub.in -.nu..sub.ref).sup.3 + . . . (2)
where .nu..sub.ref is the reference voltage from the output of a respective
integrator, and where .beta..sub.n are "n" constants chosen to produce the
best curve fit. MATLAB.TM. is, for example, a commercially available math
function that generates polynomial coefficients that define a least
squares fit polynomial for a set of input values. MATLAB may be used to
generate coefficients .alpha..sub.n and .beta..sub.n.
The Signal-to-distortion (SDR) ratio and Signal-to-noise (SNR) ratio is
determined by the following steps.
1. Determine the points along the perimeter of the of the modeled SDR.
2. Set a range of the acceptable limits around a tolerance shell of the
modeled SDR.
3. Determine the data that is representative of the contour of the SDR.
4. Calculate the average SDR value for the test device.
5. If the average SDR value is within the range of acceptable limits of the
modeled SDR then the SDR of the device is acceptable.
6. Repeat steps 1 through 5 for the SNR.
The method identified above describes, at a high level, methods which uses
data containing non-linearity and non-ideology information regarding the
integrator circuits used in over-sampled Analog-to-Digital Converters
(ADCs) to predict the Signal-to-Distortion Ratio (SDR) and Signal-to-Noise
Ratio (SNR) of the present invention.
SOFOC2 Third Order Modulator
It is first necessary to generate a simulation of the non-linear integrator
function of the device under test. A second order first order cascade
modulator architecture has been demonstrated to be effective for
predicting the non-linear performance of the integrator based device.
Prior art exists which define second order first order cascade modulator
architecture (SOFOC2) 60, for third order modulation, as illustrated in
FIG. 3. The SOFOC2 modulator 60 was chosen because it is unconditionally
stable, is tolerant to capacitor mismatch of about 5%, and tolerant to
finite op-amp gain. A maximum value for input signal "X" can be within
about 3 dB of the reference voltage without simulation overloading.
SOFOC2 modulator 60 generates an output signal "Y" which is a quantized
version of the input signal "X" plus third order shaped quantization
noise. The following is a description of the noise shaping technique
employed by modulator 60. A first stage second order modulator 61 produces
a digital output which represents the input signal, second order shaped
quantization noise, plus the additive quantization noise of the current
sample. The input to a second stage first order modulator 62 represents
the signal and second order shaped quantization noise before the addition
of the quantization noise of the current sample. The output of second
stage first order modulator 62 is the signal plus second order shaped
quantization noise from the first stage, as well as first order shaped
quantization noise from the second stage quantizer. After scaling, the
outputs of the two quantizers are subtracted at a summer 65 to yield a
signal which is the negative of the additive quantization noise of the
present sample. This signal is then doubly differentiated at a
differentiator 66 to produce the negative of the second order shaped
quantization noise of the present sample plus third order shaped
quantization noise 63 from the second stage quantizer. The resulting
signal is used to cancel the second order shaped noise coming out of the
first stage two samples later. The result of this entire process is a
quantized signal "Y" which is representative of the input signal plus
third order shaped quantization noise.
A schematic block diagram circuit 70, illustrated in FIG. 4, contains three
model capacitor integrators also referred to as switched capacitor
integrators 71, 72, and 73, and two one-bit quantizers 75 and 76. The
resulting two bits are combined digitally and a digital filter is used to
perform low-pass filtering and decimation to a lower data rate. Since
quantizer 75 in the first stage is proceeded by two integrators 71 and 72,
the quantization noise can become large as the input approaches full
scale. The quantization noise exceeding the input range of the second
stage results in a severe decrease in performance known as instability or
overload. Scaling factors "a" through "g" limit the range of the
integrator outputs and keep the loop stable. These scaling coefficients
need to meet certain criteria in order to maintain the desired noise
shaping. The following analysis is used to define the selection criteria
for coefficients "a"-"g".
The signal following the first integrator (W) is shown in equation (3). Due
to the arbitrary gain which can be associated with one-bit quantizer 75,
the scaling factor G.sub.1 is inserted before the second quantizer 72. The
output "W" of the first stage can be written as in equation (4) including
the added quantization noise Q.sub.1.
Linearized Quantizers and Arbitrary Scaling Before Quantizers.
##EQU1##
Manipulation of equation (4) yields the expression in equation (5). In
order to implement third order noise shaping, the expression in the
parentheses on the left side of equation (5) must be equal to unity, while
the coefficients associated with "X" on the right side of equation (5)
must also equal unity. This requirement causes G.sub.1 ab to be equal to
unity, G.sub.1 d to equal two, and G.sub.1 bc to equal one. One set of
coefficients which satisfies these conditions as well as restricting
integrator output signals to reasonable levels is a=1/6, b=1/4, c=1/6, and
d=1/12. The result is the transfer function shown in equation (6).
Y.sub.1 (1+(G.sub.1 d-2)z.sup.-1 +(G.sub.1 bc+1-G.sub.1 d)z.sup.-2)=G.sub.1
abXz.sup.-2 +Q.sub.1 (1-z.sup.-1).sup.2 (5)
Y.sub.1 =Xz.sup.-2 +Q.sub.1 (1-z.sup.-1).sup.2 (6)
Following the same procedure as used for analyzing the first stage, the
expression for the output from the second stage is shown in equation (7).
If the product of f and G.sub.2 is equal to one, equation (7) reduces to
equation (8). After digital scaling and subtraction of V.sub.1 the
resulting signal V.sub.3 is given in equation (9) if the product of "g",
"e", and G.sub.2 is equal to G.sub.1. After V.sub.3 is doubly
differentiated by a differentiator 74 and added to V.sub.1, the final
quantized output signal "Y" is shown in equation (10). The result is a
delayed version of the input signal "X" plus the quantization noise from
the second quantizer multiplied by "g". The values of "e", "f", and "g"
are chosen to be 1/3, 1/18, and 4 since it is easy to realize a factor of
four multiplication in the digital domain by a shift operation, and these
values allow the signal levels in the third integrator to be in the range
such that modulator 70 does not overload. The multiplication of the
quantization noise by a factor of four results in a loss of 2-bits
compared to the ideal third order modulator. The stable operation of
modulator 70 and its tolerance to capacitor mismatch and finite op-amp
gain are traded against the two-bit loss in dynamic range.
##EQU2##
Y.sub.2 =(Y.sub.1 -Q.sub.1)eG.sub.2 /G.sub.1 z.sup.31 1 +Q.sub.2
(1-z.sup.-1) (8)
V.sub.3 =gQ.sub.2 (1-z.sup.-1)-Q.sub.1 z.sup.-1 (9)
Y=gQ.sub.2 (1-z.sup.-1).sup.3 -Xz.sup.-3 (10)
The SOFOC2 architecture 70, illustrated in FIG. 4, has been successfully
implemented. The target modulator is clocked at about 5.12 MHz, and with
an oversampling ratio of 128 yields a resolution of 16-bits for a signal
bandwidth of about 20 KHz.
Signal-To-Distortion Response
Sampling methods were applied to the problem of sampling the integrator
non-linearity space of the SOFOC2 sigma-delta modulator with the goal of
determining an SDR prediction equation.
The approach was to use a sigma-delta difference equation simulator
employing the non-linear integrator model to generate random modulator
instances on an equi-SDR surface to which a surface equation is fit.
The input signal to modulator 70 which was modeled by the difference
equation simulator, was a sine-wave with a frequency in the
post-decimation base-band and amplitude 3 dB below the voltage reference
level. The SNR of SOFOC2 modulator 70 begins to decrease at this input
signal level due to overload, and is thus the maximum useable input
amplitude. The input frequency was chosen to correspond with bin 32 of the
FFT, such that up to the 15.sup.th harmonic corresponds with the base-band
frequency.
The digital output "Y" of modulator 70 in FIG. 4, was processed using an
FFT routine after widowing by a Hanning window to minimize FFT end
effects. To obtain reasonable resolution in the base-band frequency,
65,536 modulator 70 output samples were generated. To eliminate the effect
that the decimation filter roll-off has on the harmonics generated by
distortion, a decimation filter was not used. After filtering in the
frequency domain using an ideal brick-wall filter representing decimation
by 128, 512 points remained to represent the base-band spectrum. The above
described filtered digital output is also referred to in this
specification as a model data set.
A non-linear integrator model 110 is shown in FIG. 6, and the form of the
f.sub.1 and f.sub.2 distorting functions are given below.
f.sub.1 (x)=a.sub.n1 (2x.sup.2 -1)+a.sub.n2 (4x.sup.3 -3x)+a.sub.n3
(8x.sup.4 -8x.sup.2 +1) (11)
f.sub.2 (x)=a.sub.n4 x+a.sub.n5 (2x.sup.2 -1)+a.sub.n6 (4x.sup.3
-3x)+a.sub.n7 (8x.sup.4 -8x.sup.2 +1) (12)
The subscript "n" is used to identify which of the three integrators the
non-linearity coefficient is associated with. There are three coefficients
for each integrator associated with the input sampling non-linearity
f.sub.1. The linear term is omitted from the input sampling distortion
function since it has the same effect as scaling the reference which has
little impact on distortion and quantization noise. There are four
coefficients for each integrator associated with the f.sub.2 integration
distorting function in this example. There are a total of 21 non-linearity
coefficients for SOFOC2 modulator 70 (FIG. 4) with non-linear integrators
71, 72, and 73.
In order to eliminate unnecessary complexity from the surface fit, only the
non-linearities of the first integrator 71 were considered. This
simplification reduced the number of parameters from 21 to 7, and resulted
in a genetic algorithm iteration time of tens of seconds on a
SPARC-20.upsilon. workstation. The simplification has insignificant impact
in the surface fit since the non-linearities of the second 72 and third
integrators 73 are not expected to contribute significantly to distortion.
The SOFOC2 difference equation simulator with non-linear integrators
described above was used with the linear search sampling method. The
samples reside in a near equi-SDR region of the seven parameter space
formed by non-linearity coefficients a.sub.11 through a.sub.17. One
example range of the near equi-SDR region was 96.5+/-0.5 dB since 96 dB
corresponds to the desired 16-bit linearity. Each sample resulting from
the linear search sampling method consisted of the values of the seven
parameters and the resulting SDR.
A genetic algorithm surface fit algorithm 80, illustrated in FIG. 5, was
used to determine a quadratic surface equation from 2000 modulator
instances generated by the simulator. Genetic algorithm 80 comprises the
following steps: pre-compute all polynomial terms from model data set 82;
create a fixed number of random solutions (e.g. 60) 84; make sure "M" or
less terms are in each solution 86; evaluate the solutions using least
squares fit to data 88; create augmented solution set population by
preferential replication 90; randomly select two solutions from the
solution set population 92; randomly splice and recombine pairs 94;
randomly mutate some aspect of new solutions 96; make sure "M" or less
terms are in each solution 98; evaluate the new solutions 100; add each
new solution to the population if the respective new solution is better
than present member 102; remove poorer solutions if a constant population
size is desired 104; and define termination criteria 106.
In one exemplary embodiment the maximum number of terms "M" was constrained
to 24 to keep iteration time reasonable. The SDR numbers were converted
from decibels to a linear scale for the curve fit. This conversion
improves the numerical accuracy of the fit since it expands the 96-97 dB
range to a range of 63,096 to 70,095. The coefficients a.sub.11 through
a.sub.17 were scaled by 10.sup.6 before being used in the fit to minimize
the effects of truncation in the MATLAB.TM. code used in the genetic
algorithm surface fit. The form of the prediction equation in this example
is shown in equation (13). The quadratic function of the scaled
coefficients a.sub.11 through a.sub.17 represents a degradation in the SDR
of 118 dB (794,328) for SOFOC2 modulator 70 with ideal integrators at an
oversampling ratio of 128. The ratio of the sample rate to the
down-sampled data rate is known as the decimation ratio or oversampling
ratio (OSR).
SDR=794,328-f(a.sub.11, a.sub.12, a.sub.13, a.sub.14, a.sub.15, a.sub.l6,
a.sub.17)+B (13)
The fitting parameter "B" compensates for the offset in the best fit line
which maximizes the correlation coefficient between SDR from simulation
and SDR predicted by equation (13). The algorithm was run until no
improvement was observed in the correlation coefficient (R) between the
SDR from simulation and the surface equation SDR estimate. The result was
a set of at most 24 polynomial terms and associated numeric coefficients
which maximize the correlation coefficient.
The correlation coefficient is used as the fit metric since the surface
equation will be extrapolated outside the region of the fit to include a
tolerance shell, and the correlation coefficient is a measure of the
variation in the data that is accounted for by the surface equation. The
mean-square error was initially used as the fit metric, but the resulting
solution was not as good as when correlation coefficient is used. The
reason that correlation coefficient is a better fit metric than
mean-squared error is that the response of the modulator SDR to changes in
non-linearity is not quadratic and can only be fit by a quadratic equation
at a single point.
The initial solution set population of the improvement in genetic algorithm
80 (FIG. 5) contained a good solution such that the improvement in the
best solution was minor, converging to R=0.86 in 200 generations. A
near-best solution is likely to exist in the initial solution set
population since there are four terms which dominate the fit and a
solution set population of 60 solutions, each with 24 terms, will likely
contain one solution with the four dominant terms. The linear search
sampling method will be shown to under-sample part of the parameter space
such that certain features are not represented by the data and thus cannot
be fit. The data does not contain information on fine features necessary
for accurate SDR prediction over the expected range of coefficients
a.sub.11 through a.sub.17. The lack of the fine features makes finding the
best fit easy since four terms dominate the response. The mean value of
"R" for the solution set population increases monotonically with
generations as the characteristics of the best solution proliferates all
solutions until the solution set population is homogeneous.
The best solution consisted of the 14 terms and associated coefficients
illustrated in Table 4.1. The non-linearities associated with input
sampling (a.sub.11, a.sub.12, and a.sub.13) have the largest impact on
SDR, as evidenced by the relative magnitude of the coefficients associated
with the quadratic terms of these parameters. The interaction between the
quadratic and fourth-order terms of the n-dimensional Chebychev polynomial
function associated with a.sub.11 and a.sub.13 is also significant. The
interaction is due to the presence of a squared term in the first and
third non-linear terms of the Chebychev polynomial as shown in equation
(11). Domination of the SDR by the coefficients of f.sub.1 is not
unexpected since the signal seen by the f.sub.2 distorting function
resembles the derivative of input signal "X" (FIG. 4) plus quantization
noise. The differentiation significantly attenuates the component of the
input signal "X" to f.sub.2 at the input signal frequency used since the
input signal frequency is substantially lower than the sample frequency in
the over-sampling scheme.
TABLE 4.1
Surface Fit Equation Terms and Coefficients
Using Linear Search Sampling
Term Coefficient
a.sub.11.sup.2 7.320
a.sub.12.sup.2 5.740
a.sub.13.sup.2 10.050
a.sub.15.sup.2 0.004
a.sub.16.sup.2 0.004
a.sub.11 a.sub.13 -12.760
a.sub.11 a.sub.14 0.090
a.sub.11 a.sub.16 -0.210
a.sub.12 a.sub.13 0.030
a.sub.12 a.sub.15 -0.010
a.sub.12 a.sub.17 0.120
a.sub.13 a.sub.14 -0.060
a.sub.13 a.sub.16 0.170
a.sub.16 a.sub.17 0.003
The SDR prediction equation was applied to the eight modulator instances
associated with the design of experiment (DOE). The non-linearity
coefficients extracted from SPICE.TM. circuit simulations of the
non-linear integrators described above were used in the difference
equation sigma-delta simulator and the SDR obtained. Table 4.2 compares
the SDR from simulation and that predicted by the surface equation.
TABLE 4.2
Simulated and Predicted SDR from Data Generated Using
Linear Search Sampling
Case Simulated SDR Predicted SDR
1 110.2 dB 94.7 dB
2 97.7 97.6
3 94.6 93.4
4 108.0 99.4
5 96.7 95.6
6 101.8 98.5
7 96.2 95.4
8 97.0 96.9
There was substantial discrepancy between the simulated SDR and that
predicted by the equation. The discrepancies appeared larger when the SDR
was higher than 96 to 97 dB where the fit was performed. To understand the
relationship between the modulator response and the prediction equation, a
comparison based upon randomly chosen modulator instances was performed.
Coefficients for the surface equation illustrated in Table 4.1 was tested
by randomly generating modulator instances using the difference equation
sigma-delta simulator. Vectors in the seven dimension space were randomly
chosen and the simulator run to determine the SDR of the resulting
modulator instance. Based on the range of non-linearity coefficients from
SPICE.TM. simulations of first integrator 71, the coefficients of f.sub.1
were selected from a uniform distribution ranging from -10.sup.-5 to
+10.sup.-5, and the coefficients of f.sub.2 were selected from a uniform
distribution ranging from -10.sup.-4 to +10.sup.-4. The resulting 2000
modulator instance SDRs ranged from 87.2 dB to 110.7 dB. The SDR histogram
of the test set is nearly centered around an SDR of 96.5 dB, and therefore
a robust test of the prediction equation near the region of the fit. The
surface equation was used to predict the SDR from the non-linearity
coefficient values of the test set.
The relationship between the predicted and simulated SDR becomes highly
non-linear as the SDR moves out of the 96+/-0.5 dB region where the fit
was performed. When the SDR is significantly higher or lower than 96.5 dB,
the predictor underestimates the SDR, but does so in a monotonic and
consistent fashion. The relationship is monotonic, and therefore the lack
of prediction accuracy away from the fit region is inconsequential when
the equation is used in design optimization procedures. Monotonicity
allows a gradient based optimization approach to seek the desired
performance. From 500 points in the region of the fit the RMS error in the
prediction accuracy was determined to be 0.25 dB.
The feature which differentiates the modulator instance represented by the
first row of Table 4.2 is that the magnitude of the coefficients of
f.sub.2 are larger than those of the other rows, with a.sub.15 and
a.sub.17 equal to approximat | | |
