A power conservation system which provides for fast and efficient transitions between fast and slow processor clocking speeds. The slow processor clocking speed minimizes power consumption during periods of processor inactivity (idle states) or low priority execution. The fast processor clocking speeds are utilized during periods of processor activity (active states) or high priority execution. Used in conjunction with a context-sensitive processor, the power conservation system is able to monitor the state of the processor and modify the processor clocking speed accordingly.
A power reduction device which includes a first clocking device for generating a first clocking signal, a second clocking device for generating a second clocking signal, a synchronizer device for receiving the first and second clocking signals and being responsive to a first select signal and to a second control signal wherein upon receipt of either of the select or control signals, the synchronizing device generating a synchronized signal without a glitch therefrom wherein the synchronized signal corresponding to either the first or second clocking signals.
A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter based on the relative speed. In one embodiment, an integrated circuit may include a ring oscillator, a shift register having a clock input coupled to an output of the ring oscillator, and compare logic coupled to an output of the shift register. The shift register is enabled in response to initiating a memory access to a memory and disabled in response to completing the memory access. The compare logic provides a relative speed indicator representative of a relative speed of the memory.
An electronic device includes a central processing unit (CPU) and a main system bus. The central processing unit operates at a first clock frequency and the main system bus operates at a second clock frequency that is lower than the first clock frequency, responsive to the electronic device being in an active mode. Both the central processing unit and the main system bus are operated at a third clock frequency that is lower than the second clock frequency, responsive to the electronic device being in an idle mode. An operating voltage of the central processing unit also may be decreased responsive to the electronic device being in the idle mode.
The present invention provides apparatus and methods to perform thermal management in a computing environment. Thermal attributes are associated with operations and/or processing components. The components have thermal thresholds that should not be exceeded. In a preferred embodiment, an operation can be transferred from one component to another component if the thermal threshold is exceeded during execution by the first component.
A method including searching for a communication channel by activating a receiver having a radio frequency (RF) module and a baseband module for storing a portion of received signals within a first time period, de-activating the RF module of the receiver, and background processing the portion of the received signals with a variable clock rate within a second time period.
