A data processing apparatus for performing data communication via a digital interface includes a receiver circuit for receiving reception data and a transmitter circuit for transmitting transaction data corresponding to the reception data. The transaction data includes a source ID representative of a source node and a destination ID representative of a destination node. ID information of the data processing apparatus is controlled by a management control circuit. An ID setting circuit sets the ID information from the management control circuit as the source ID of the transaction data, and sets a source ID included in the reception data as the destination ID of the transaction data.
There is disclosed a communication system and communication protocol in which a source node and one or more destination nodes are logically connected, and a connection ID for identifying the logical connection relationship is used to control data communication between the nodes. There is also disclosed an efficient communication system and communication protocol in which an optimum time interval between a time to transmit an i-th (i being an optional integer) data and a time to transmit an (i+1)-th data can be set. There is further disclosed a communication system and communication protocol in which when the i-th data is not normally received, retry is inhibited only for a predetermined time to prevent the retry from unnecessarily occurring between a destination node slow in receiving process and a source node fast in transmitting process.
Provided is a communication system for logically connecting a source node and one or more destination nodes, and for controlling data communication between the individual nodes by employing a connection ID that is used to identity the logical connection relationship. The communication system may comprise a source node adapted to transmit data packets, a destination node adapted to receive the data packets transmitted from the source node, and a controller adapted to manage a logical connection between the source node and the destination node, the destination node being adapted to abort communication between the source node and the destination node if the destination node received an abort packet transmitted from the controller, and the destination node being adapted to disconnect the logical connection after the communication is aborted by the abort packet. The source node itself, and methods of using the system and that node, are also individual aspects of what is disclosed.
An objective of the present invention is to provide a data transfer control device and electronic equipment which make it possible to reduce processing overheads in the firmware and implement high-speed data transfer. In a data transfer control device in accordance with the IEEE 1394 standard, the header of a packet is written to a header area, the ORB (data for SBP-2) of the packet is written to an ORB area, and the stream (data for the application layer) of the packet is written to a stream area. The stream area is managed by hardware in accordance with full and empty signals. Indication information is comprised within a transaction label tl of a request packet, and the header, ORB, and stream of a response packet are written to areas indicated by the indication information comprised within tl, when the response packet is received. The device is also provided with registers TSR and TER that contain addresses TS and TE for securing a transmission area in the stream area and registers RSR and RER that contain addresses RS and RE for securing a reception area therein.
An objective of the present invention is to provide a data transfer control device and electronic equipment which make it possible to reduce processing overheads in the firmware and implement high-speed data transfer. In a data transfer control device in accordance with the IEEE 1394 standard, the header of a packet is written to a header area, the ORB (data for SBP-2) of the packet is written to an ORB area, and the stream (data for the application layer) of the packet is written to a stream area. The stream area is managed by hardware in accordance with full and empty signals. Indication information is comprised within a transaction label t1 of a request packet, and the header, ORB, and stream of a response packet are written to areas indicated by the indication information comprised within t1, when the response packet is received. The device is also provided with registers TSR and TER that contain addresses TS and TE for securing a transmission area in the stream area and registers RSR and RER that contain addresses RS and RE for securing a reception area therein.
A communication system, in which data transmission is interrupted for a bus reset, includes a source and a destination with a receiving buffer. The source is adapted to transmit a segment of data to the destination using address information corresponding to a part of the receiving buffer of the destination. Transmission of the data is interrupted if a process of resetting a bus between the source and the destination occurs. After the process of resetting the bus ends, the transmission of the data resumes without retransmitting data determined by the source to be already stored in the receiving buffer.
