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Fast scannable output latch with domino logic input
   
Document Number
US Patent 6272654
Issued Date
August 7, 2001
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Abstract
A scannable fast domino output latch is provided. A scannable latch circuit includes a scan logic receiving a scan data input and a scan data clock. The scannable latch circuit includes a transistor stack receiving a data input and receiving a system clock. A first inverter is connected to the transistor stack. The first inverter provides a latch output. A feedback path logic is connected across the first inverter. The feedback path logic is activated responsive to both the system clock and the scan data clock. Improved performance is provided by eliminating the transfer gate and active feedback from the critical path of the scannable latch circuit. The feedback path logic is activated when both the system clock and the scan data clock are low.
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Fast scannable output latch with domino logic input - US Patent 6272654 Drawing
Drawing from US Patent 6272654
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Number of Claims:
12
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Published
August 7, 2001
Application Number
09/262,797
Filed
March 4, 1999
US Classification
714/724  
Int'l Classification
H03K   3/00   (20060101)   H03K   3/037   (20060101)   G01R   31/28   (20060101)   G01R   31/3185   (20060101)   H03K   3/356   (20060101)  
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USPTO Field of Search
714/724  
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