Silicon multi-chip module packaging with integrated passive components and method of making

Claims

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. A chip carrier comprising:

an interposer element comprising a semiconductor substrate layer and at least one insulating layer on a surface of said substrate layer, said insulating layer supporting at least one passive circuit element which is separated from said substrate layer by a portion of said insulating layer, said portion of said insulating layer having a thickness which is sufficient to electrically shield said at least one passive circuit element from said substrate layer.

2. The chip carrier of claim 1, further comprising at least one integrated circuit chip attached to said interposer element and electrically connected to said at least one passive circuit element.

3. The chip carrier of claim 2, wherein said semiconductor substrate layer comprises a silicon layer.

4. The chip carrier of claim 3, wherein said at least one insulating layer comprises an oxide layer.

5. The chip carrier of claim 4, wherein said oxide layer includes silicon dioxide (SiO.sub.2).

6. The chip carrier of claim 5, wherein said oxide layer has a thickness within a range of three to five microns.

7. The chip carrier of claim 3, wherein said at least one insulating layer comprises a polyamide layer.

8. The chip carrier of claim 3, wherein said at least one passive element is embedded within said at least one insulating layer.

9. The chip carrier of claim 3, wherein said at least one passive element is formed on said at least one insulating layer.

10. The chip carrier of claim 3, further comprising a metallization pattern on or within said insulating layer connected with said at least one passive circuit device.

11. The chip carrier of claim 3, wherein said at least one insulating layer includes a plurality of passive circuit elements, said plurality of passive circuit elements separated from said substrate layer by a portion of said at least one insulating layer, said portion of said at least one insulating layer having a thickness such that said plurality of passive circuit elements are electrically shielded from the conductance of said substrate layer.

12. The chip carrier of claim 11, wherein said plurality of passive circuit elements includes a resistor element.

13. The chip carrier of claim 12, wherein said resistor element is a thin film metal resistor.

14. The chip carrier of claim 13, wherein said plurality of passive circuit elements includes a capacitor element.

15. The chip carrier of claim 14, wherein said capacitor element is a thin film capacitor.

16. The chip carrier of claim 15, wherein said thin film capacitor includes a dielectric layer.

17. The chip carrier of claim 16, wherein said dielectric layer is an oxide composition.

18. The chip carrier of claim 16, wherein said dielectric layer is an oxide-nitride-oxide composition.

19. The chip carrier of claim 15, wherein said plurality of passive circuit elements includes an inductor element.

20. The chip carrier of claim 19, wherein said inductor element is a spiral inductor.

21. The chip carrier of claim 20, wherein said plurality of passive circuit elements form at least one passive circuit device, said passive circuit device having at least one of said plurality of passive circuit elements and electrically connected to said at least one integrated circuit chip.

22. The chip carrier of claim 21, wherein said plurality of passive circuit elements form at least one passive circuit device used in radio frequency (RF) communications systems.

23. The chip carrier of claim 22, wherein said interposer element and said at least one integrated circuit are arranged to form circuitry used in RF communications systems.

24. The chip carrier of claim 23, wherein said at least one passive circuit device comprises a load amplifier.

25. The chip carrier of claim 23, wherein said at least one passive circuit device comprises a broad band amplifier.

26. The chip carrier of claim 23, wherein said at least one passive circuit device comprises an oscillator.

27. The chip carrier of claim 26, wherein said oscillator is a voltage controlled oscillator.

28. The chip carrier of claim 23, wherein said at least one integrated circuit chip comprises a chip having at least one logic device electrically connected to said interposer element.

29. The chip carrier of claim 28, wherein said chip contains analog circuitry.

30. The chip carrier of claim 28, wherein said at least one logic device is a transistor.

31. The chip carrier of claim 30, wherein said chip contains digital circuitry.

32. The chip carrier of claim 31, wherein said chip is a microprocessor.

33. The chip carrier of claim 31, wherein said chip is a memory chip.

34. The chip carrier of claim 29, wherein said at least one integrated circuit chip is attached to said interposer element by solder joints.

35. The chip carrier of claim 34, wherein said at least one integrated circuit chip is attached to said interposer element through flip-chip bonding.

36. The chip carrier of claim 35, wherein said solder joints have varying compositions such that each of said solder joints has a selective melting temperature.

37. The chip carrier of claim 29, wherein said at least one integrated circuit chip is attached to said interposer element by a conductive adhesive substance.

38. The chip carrier of claim 29, wherein a bonding agent is located in the area between the said at least one integrated circuit chip and said insulating layer.

39. The chip carrier of claim 38, wherein said bonding agent is epoxy.

40. The chip carrier of claim 29, wherein said chip carrier is encapsulated to form a circuit package, said circuit package having conducting leads on an outer side of said package.

41. The chip carrier of claim 40, further comprising conductive leads connecting the chip carrier to said conductive package leads of said circuit package.

42. The chip carrier of claim 2, wherein said interposer element includes first and second insulating layers on opposing surfaces of said substrate.

43. The chip carrier of claim 42, wherein each of said first and second insulating layers has at least one passive circuit element separated from said substrate layer by a portion of said first and second insulating layers having a thickness such that each of said at least one passive circuit elements is electrically shielded from the conductance of said substrate layer.

44. The chip carrier of claim 43 wherein said first and second insulating layers include a plurality of passive circuit elements.

45. The chip carrier of claim 44, wherein at least one of said first and second insulating layers has at least one active circuit element.

46. The chip carrier of claim 1, wherein said substrate layer is comprised of gallium-arsenide.

47. The chip carrier of claim 46, wherein said insulating layer is comprised of gallium-arsenide-oxide.

48. A chip carrier comprising:

an interposer element comprising a semiconductor substrate layer and at least one insulating layer on a surface of said substrate layer, said insulating layer supporting at least one passive circuit element which is separated from said substrate layer by a portion of said insulating layer, said portion of said insulating layer having a thickness which is sufficient to electrically shield said at least one passive circuit element from said substrate layer;

at least one integrated circuit chip attached to said interposer element and electrically connected to said at least one passive circuit element; and

said interposer element and said at least one integrated circuit contain electrical elements which form circuitry for use in radio frequency (RF) communications systems.

49. The chip carrier of claim 48, wherein at least one of said plurality of insulating layers comprises an oxide layer.

50. The chip carrier of claim 49, wherein said oxide layer includes silicon dioxide (SiO.sub.2).

51. The chip carrier of claim 50, wherein said oxide layer has a thickness within a range of three to five microns.

52. The chip carrier of claim 48, wherein at least one of said plurality of insulating layers comprises a polyamide layer.

53. The chip carrier of claim 48, wherein at least one of said plurality of passive elements is embedded within said at least one insulating layer.

54. The chip carrier of claim 48, wherein at least one of said plurality of passive elements is formed on said at least one insulating layer.

55. The chip carrier of claim 48, further comprising a metallization pattern on or within said insulating layer connected with said at least one passive circuit device.

56. The chip carrier of claim 55, wherein said plurality of passive circuit elements includes a resistor element.

57. The chip carrier of claim 56, wherein said resistor element is a thin film metal resistor.

58. The chip carrier of claim 57, wherein said plurality of passive circuit elements includes a capacitor element.

59. The chip carrier of claim 58, wherein said capacitor element is a thin film capacitor.

60. The chip carrier of claim 59, wherein said thin film capacitor includes a dielectric layer.

61. The chip carrier of claim 60, wherein said dielectric layer is an oxide composition.

62. The chip carrier of claim 60, wherein said dielectric layer is an oxide-nitride-oxide composition.

63. The chip carrier of claim 60, wherein said plurality of passive circuit elements includes an inductor element.

64. The chip carrier of claim 63, wherein said inductor element is a spiral inductor.

65. The chip carrier of claim 64, wherein said plurality of passive circuit elements form at least one passive circuit device, said passive circuit device having at least one of said plurality of passive circuit elements and electrically connected to said at least one integrated circuit chip.

66. The chip carrier of claim 65, wherein said plurality of passive circuit elements form at least one passive circuit device used in radio frequency (RF) communications systems.

67. The chip carrier of claim 66, wherein said at least one passive circuit device comprises a load amplifier.

68. The chip carrier of claim 66, wherein said at least one passive circuit device comprises a broad band amplifier.

69. The chip carrier of claim 66, wherein said at least one passive circuit device comprises an oscillator.

70. The chip carrier of claim 69, wherein said oscillator is a voltage controlled oscillator.

71. The chip carrier of claim 66, wherein said at least one integrated circuit chip comprises a chip having at least one logic device electrically connected to said interposer element.

72. The chip carrier of claim 71, wherein said chip contains analog circuitry.

73. The chip carrier of claim 71, wherein said at least one logic device is a transistor.

74. The chip carrier of claim 73, wherein said chip contains digital circuitry.

75. The chip carrier of claim 74, wherein said chip is a microprocessor.

76. The chip carrier of claim 74, wherein said chip is a memory chip.

77. The chip carrier of claim 71, wherein said at least one integrated circuit chip is attached to said interposer element by solder joints.

78. The chip carrier of claim 77, wherein said at least one integrated circuit chip is attached to said interposer element through flip-chip bonding.

79. The chip carrier of claim 78, wherein said solder joints have varying compositions such that each of said solder joints has a selective melting temperature.

80. The chip carrier of claim 71, wherein said at least one integrated circuit chip is attached to said interposer element by a conductive adhesive substance.

81. The chip carrier of claim 71, wherein a bonding agent is located in the area between the said at least one integrated circuit chip and said insulating layer.

82. The chip carrier of claim 81, wherein said bonding agent is epoxy.

83. The chip carrier of claim 71, wherein said chip carrier is encapsulated to form a circuit package, said circuit package having conducting leads on an outer side of said package.

84. The chip carrier of claim 83, further comprising conductive leads connecting the chip carrier to said conductive package leads of said circuit package.

85. The chip carrier of claim 71, wherein said interposer element includes first and second insulating layers on opposing surfaces of said silicon substrate.

86. The chip carrier of claim 85, wherein each of said first and second insulating layers has a plurality of passive circuit elements separated from said silicon substrate layer by a portion of said first and second insulating layers having a thickness such that said plurality of passive circuit elements are electrically shielded from the conductance of said silicon substrate layer.

87. The chip carrier of claim 86, wherein at least one of said first and second insulating layers has at least one active circuit element.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to multiple function semiconductor devices and, in particular, to silicon packaging for holding semiconductor devices and passive electronic components in close proximity.

2. Description of the Related Art

Portable wireless communications are a rapidly growing segment of consumer communication devices which are designed to operate in the radio frequency (RF) range. Many of the se devices now operate in the L-band, or between 1-2.4 Gigahertz. In light of the increased demand for RF devices and the numerous digital-based communications systems which are currently available, an integrated package capable of delivering RF and digital communications has become desirable. Integrated portable communications devices would allow users to utilize one device for operating in a variety of communications systems. In addition, the integration of components offers attractive savings in terms of packaging size, cost, and energy requirements when compared to the operation of electrically and physically separate systems within one device.

The successful integration of RF devices into known digital communications systems requires the implementation of RP components within digital systems. The group of essential RF components, the front end circuitry of RF devices, generally includes passive electronic components. One of the benefits of using passive components in front end circuitry is that they experience relatively low loss due to the absence of noise from power sources. In addition, passive components may be processed at low cost using relatively few steps and common materials. Passive components include inductors, capacitors, and resistors. These components may be used to provide RF tuned amplifiers, oscillators, and optimizing broad-band filters which are required in RF communication systems.

Integrating RF and digital circuitry on a single package will place restrictions upon the composition and construction of the included components. A key component to the viability of personal communication and similar devices is the conservation of power to preserve battery life. Therefore, integrated digital and RF components, such as inductors, resistors and capacitors, should be able to operate in low power environments. The restriction of having a low power supply has, in the past, limited the advance of integrated systems.

In addition, the production of an integrated package would theoretically be optimized by using known integrated circuit (IC) processes for the manufacture of such systems. The existence of a variety of known IC fabrication processes in addition to the inherent speed, low power consumption, and reduced size of IC make it ideal for use in integrated devices.

Resistors and capacitors form the building blocks of a variety of RF devices. The resistivity of a material is dependant upon its composition and environment. For RF applications, resistors must have precise, low fluctuation resistivity values. For use in RF devices a resistor must be able to operate at relatively low resistivity values due to the reduced voltage available from a power supply as compared to non-integrated IC devices. Similarly, capacitors for RF devices must have predictable values with low tolerances. Construction of capacitors and resistors for use in an integrated system while retaining the necessary RF characteristics is problematic due to the opposing concerns of RF-constrained component operating parameters with the size and power supply parameters of integrated circuits.

The most challenging RF component to adapt to an integrated system is the inductor. Inductors are an essential component of a variety of RF devices, including RF amplifiers which employ a tuned load. RF amplifiers supply gain using inductor-capacitor resonance to nullify device and parasitic capacitance at the center frequency. Such devices also form a secondary filter for noise and out-of-band signals. Inductors in integrated systems must be able to provide relatively large inductance values, ideally greater than 10 nH (dependent upon frequency range) while being physically small such that a compact architecture can be achieved. The inductance value is dependent in large part upon the geometry of the inductor itself. In fact, the inclusion of passive components will often dictate the size of system more than any other part. Thus, design of high valued inductors within compact spaces is necessary for successful RF/digital integration.

Capacitors and inductors in RF front end circuitry must also be tuned to deliver high quality (Q) factors at the operational frequency. A Q factor is dependent upon resistance and either capacitance or inductance, depending upon the component being measured. Maximizing Q while recognizing the necessary limitations set by theoretically effective integrated systems (size, power, etc.) has proven difficult. In addition, inductors and capacitors experience rapid deterioration of performance near their self resonating frequency. A self resonating frequency will vary depending upon the material composition, the size of the device, and the devices surroundings. Many current RF systems operate at frequencies ranging from 1.0 to 2.5 GHz. Therefore, the self resonating frequency of a inductor or capacitor element should be significantly higher than the operating frequency to avoid deterioration of the effectiveness of the element.

Various methods have been used to integrate RF components into IC processes. Gallium-Arsenide (GaAs) substrates are the most common platforms for fabricating RF passive devices in currently known systems. GaAs has several beneficial qualities which make it attractive for use in integrating RF components. Due to the semi-insulating qualities of GaAs, certain passive elements having low to medium Q factors (5-15) may be placed on chip without experiencing severe effect deterioration. However, GaAs-based RF components suffer from limited Q factors due to inherent problems with on-chip noise and physical limitations. In addition, the on-chip noise contributes to increased fluctuations in inductance and capacitance values, rendering them fairly unpredictable. The resulting GaAs-based systems exhibit properties which are unacceptable if the device is to function in future integrated communications networks which will require predictability and high Q factors.

Silicon-based passive components theoretically offer the best combination of qualities for use in integrated systems. Silicon is a relatively inexpensive material for which numerous processing systems have been developed. Silicon bipolar processes have threshold frequencies, from 2-50 GHz, which are sufficient to supply gain through the most common RF communications frequencies. In addition, silicon IC's are capable of higher complexity than GaAs systems, allowing for the possibility of more compact integration.

Though attractive, silicon technology raises several barriers to successful integration of RF and digital technology. Silicon substrates suffer from lower substrate resistivity when compared to GaAs. The inherent conductance of the silicon substrate induces loss and limits inductors and capacitors to poor Q factors. Encasing the transmission line conductors in the oxide insulators used in silicon integrated circuits increases the stray capacitance and lowers the self resonance frequency. Thus, as the frequency received by an integrated communications system is increased, the inductance will decrease. Losses in the conductive silicon substrates are increased by the high dielectric constant of the insulators under the conductors, and relatively large values of stray capacitive coupling to the silicon substrate. Resistors, though effected by their surroundings, generally perform well when deposited on a silicon substrate. Poor Q value in capacitors and inductors and RF/digital line conductor loss have created significant barriers to fabrication of a viable integrated system. Though several attempts to solve these problems have been made, no device has addressed each of these concerns sufficiently. The effect of a silicon substrate on passive device performance is described in Integrated Passive Components in MCM-Si Technology and their Applications in RF-Systems, IEEE 1998 International Conference on Multichip Module and High Density Packaging, 1998 (Hartung). A multilayer construction containing a one micron thick silicon dioxide layer as an insulator was formed on a silicon substrate and significant performance loss was found in passive devices formed within the multilayer construction due to the low resistivity of the silicon substrate.

Several prior art schemes have been developed to deal with problems inherent in silicon-based passive element fabrication and integration. One solution utilizes an air bridge between an inductor and the silicon substrate as described in U.S. Pat. No. 5,539,241 (Abidi et al.). FIG. 8 shows a typical air bridge construction wherein a cavity 254 is etched in substrate 250. Inductor elements 256 are then deposited in oxide layer 252 such that the inductor elements 256 are located above the cavity 254. The cavity 254, filled with air, acts as an insulator between the inductors 256 and the semiconductor substrate 250 and, therefore, reduces the negative effects which come from having a silicon substrate.

Similarly, the use of suspended wire spans is described in A14V, 5mW, 1.8GHz, Balanced Voltage-Controlled Oscillator with an Integrated Resonator (Hitko, et al.), to create inductors for use in silicon-based voltage controlled oscillators (VCO). Shown in FIGS. 9a and 9b, the design is comprised of metal wires 304 suspended from the surface of the substrate 300 by the use of pads 302. The wires 304 are formed in a U shape, shown in FIG. 9b, and are suspended above substrate 300 such that air acts as an insulator between the silicon substrate 300 and the wires 304. The metal wires 304 are electrically connected to circuit elements contained within the substrate 300 through contacts 306.

Higher Q inductors have also been developed in silicon-based substrates using a five to six level metal BiCMOS technology, as described in Integrated RF and Microwave Components in BiCMOS Technology, 43 IEEE Transactions on Electron Devices 9, 1996 (Burghart). However, the implementation of spiral inductors using this technology is not practical in light of the fact that the five to six levels of metal architecture needed is far in excess of the two to four levels most commonly used in CMOS construction processes.

Integration of spiral inductors has also been accomplished for discrete multi-chip modules (MCM-D) using LSI technology. As described in Low-Complexity MCM-D Technology with Integrated Passives for High Frequency Applications, IEEE 1998 (Samber et al.), the process uses a double metal back-end process on isolated high-ohmic silicon and incorporates a resistor layer, thin film resistors, capacitors, and inductors.

Integration of passive components into MCM-Si technology has proven to be difficult. Silicon is preferred because it is relatively easy to process, there are known methods for processing , and it achieves good flatness and reduced roughness over comparable materials. Passive devices in silicon would also have similar thermal coefficients to the chip die, ensuring environmental compatibility. U.S. Pat. No. 5,770,476 teaches the use of an interposer constructed of a conductor-insulator-conductor on which passive devices are created. None of the described methods produces silicon-based system within which high-Q inductors and capacitors can be placed in close proximity to a chip containing digital circuitry.

SUMMARY OF THE INVENTION

The present invention provides a multi-chip module that is able to overcome some of the problems attendant the integration of RF and digital circuitry within the same packaging.

The above and other features and adv