A system and method for synchronizing processors simulated in an architectural simulator for a multiprocessor environment. A synchronous breakpoint is set at a predetermined address location and a code portion targeted for execution on the target multiprocessor environment is launched on the simulator from a fixed location. Upon automatically stepping through a list of processors initialized in the simulator until each of the processors reaches the synchronous breakpoint, run control is returned to the user only after all processors have achieved a synchronous state. Debug operations may ensue thereafter by utilizing a debugger integrated with the architectural simulator.

A DMA controller has both a receiving portion and a sending portion and may be used in a modem or other data transmission context. The DMA controller is intended to provide to or receive from data samples on a bus that may or may not be available. For the case when the bus is available, samples of data are either sent to or received from proper memory locations. When the bus is not available, the number of the samples that are missed due to the bus not being available is stored. This count is then used to ensure that the samples that are provided or received when the bus becomes available are stored in or read from the proper location to provide the samples at the proper time. The locations in which the samples were lost are provided with predetermined values.

An apparatus, and a corresponding method, are used for seeding differences in lock stepped processors, the apparatus implemented on two or more processors operating in a lock step mode. Each of the two or more processors comprise a processor-specific resource operable to seed the differences, a processor logic to execute a code sequence, in which an identical code sequence is executed by the processor logic of each of the two or more processors, and an output to provide a result of execution of the code sequence. The processor outputs, based on execution of the code sequence is provided to a lock step logic operable to read and compare the output of each of the two or more processors.

A computer cluster includes a network plane and a processing plane. In the cluster, the network plane is formed by at least one network computer, which is configured to assign a time tag to incoming request data. The processing plane is composed of at least two processing computers, which are supplied in parallel with the request data from the network plane. Each processing computer is configured to process the request data in a subsequent processing step, if the current value of the time tag falls within a respective significant value range. An "implicit synchronisation" of the computers is thus achieved in a simple manner.

An apparatus, and a corresponding method, are used for seeding differences in lock stepped processors, the apparatus implemented on two or more processors operating in a lock step mode, wherein each of the two or more processors comprise a processor-specific resource operable to seed the differences, a processor logic to execute a code sequence, wherein an identical code sequence is executed by the processor logic of each of the two or more processors, and an output to provide a result of execution of the code sequence. The processor outputs, based on execution of the code sequence is provided to a lock step logic operable to read and compare the output of each of the two or more processors.