A logic emulation system that verifies a target logic circuit and evaluates its performance efficiently divides the design data of a target logic circuit into a plurality of small-scale logic circuits and a connection circuit for interconnecting the small-scale logic circuits, thereby creating an equivalent circuit of the target logic circuit. The logic emulation system judges, when a logical design change to the target logic circuit prompts the comparison of the data of the equivalent circuit of the logic circuit before the logical change with the data after the logical change, whether it is feasible to implement the design data on the logically changed logic circuit by adding one or more small-scale logic circuits, and by altering the connection circuit accordingly. When the implementation of the design data on the logically changed logic circuit is judged to be feasible, the equivalent circuit of the logically changed logic circuit is generated by resorting to the above measures and without modifying the existing equivalent circuit.
This is a continuation application of U.S. Ser. No. 08/969,110, filed on Nov. 12, 1997 now U.S. Pat. No. 6,070,005, which is a continuation application of U.S. Ser. No. 08/483,987, filed Jun. 7, 1995 now U.S. Pat. No. 5,699,283.
An integrated circuit device includes a semiconductor substrate having an interlayer insulating layer thereon and a first junction block embedded in the interlayer insulating layer. The first junction block includes a first plurality of conductive junction traces located side-by-side within the interlayer insulating layer and a corresponding first plurality of pairs of conductive vias connected to opposite ends of respective ones of the first plurality of conductive junction traces. The first junction block also includes a dummy conductive trace located adjacent the first plurality of conductive junction traces and a pair of dummy conductive vias connected to opposite ends of the dummy junction trace. The integrated circuit device further includes a plurality of upper metallization traces routed on the interlayer insulating layer. The upper metallization traces are configured to electrically connect with the first plurality of pairs of conductive vias and maintain the dummy conductive trace and the pair of dummy conductive vias in an unused and electrically floating condition.
A method for designing an integrated circuit having analog and digital circuit portions is disclosed. The method involves providing an emulation circuit, which preferably comprises a number of gates equivalent to a number of gates in the digital circuit portion, affixing the emulation circuit on a test substrate together with a version of the analog circuit portion having at least some of the defined functions of the analog circuit portion, and then testing the analog circuit version.
Data processing resources are distributively provided to an emulation system to locally and correspondingly generate configuration signals to configure selected ones of reconfigurable logic and interconnect resources of corresponding collections of reconfigurable logic and interconnect resources, to emulate corresponding partitions of an IC design. In one embodiment, the distributed data processing resources further locally and correspondingly determine inteconnect routing within the selected ones of the reconfigurable logic resources of the corresponding collections of reconfigurable logic resources. In one embodiment, the distributed data processing resources are disposed on logic boards having emulation ICs that include the reconfigurable logic and interconnect resources. In other embodiments, at least some of the distributed data processing resources are disposed on the emulation ICs. The board and IC disposed distribtued data processing resources cooperatively perform the earlier mentioned distributed and corresponding generation of configruation signals and interconnect routing determination.
A method for designing an integrated circuit having analog and digital circuit portions is disclosed. The method involves providing an emulation circuit, which preferably comprises a number of gates equivalent to a number of gates in the digital circuit portion, affixing the emulation circuit on a test substrate together with a version of the analog circuit portion having at least some of the defined functions of the analog circuit portion, and then testing the analog circuit version.
Serializing and deserializing circuits are provided on an emulator circuit board to group input and output signals of programmable logic devices for routing through a cross point switch. In one instance, the input and output signals of the programmable logic devices are time-multiplexed signals of virtual interconnections. The cross point switch can be configured for static or dynamically scheduled operations.
