System and method for on-chip filter tuning

What is claimed is:

1. An integrated circuit chip comprising:

a first adjustable on-chip filter having a first plurality of selectable capacitors that determine its center frequency;

a second adjustable on-chip filter having a second plurality of selectable capacitors that determine its center frequency;

means for selecting a number of the first plurality of capacitors to adjust the first filter to a desired center frequency; and

means for transferring the selection of the first plurality of capacitors to the second plurality of capacitors to adjust the second filter to a center frequency proportional to the desired frequency.

2. The integrated circuit of claim 1, in which the transferring means adjusts the second filter to a center frequency that is equal to the desired frequency.

3. The integrated circuit of claim 1, in which the transferring means includes frequency scaling means that adjusts the second filter to a center frequency that is a multiple of the desired frequency.

4. The integrated circuit of claim 1, in which the multiple is a whole number.

5. The integrated circuit of claim 1, in which the multiple is a fraction.

6. The integrated circuit of claim 1, in which the transferring means operates after the number of first capacitors is selected.

7. The integrated circuit of claim 1, in which the first plurality of capacitors is selectable by switching the individual capacitors on and off and the selecting means comprises:

a local oscillator (LO);

means for coupling the LO to the first filter;

means for comparing the output of the LO to the output of the first filter; and

means for switching combinations of the first plurality of capacitors on and off until the outputs of the LO and the first filter have the same center frequency.

8. The integrated circuit of claim 7, in which the first plurality of capacitors are switched off after the selection of the first plurality of capacitors is transferred to the second plurality of capacitors.

9. The integrated circuit of claim 7, in which the switching means switches on and off combinations of the first plurality of capacitors such that the center frequency of the first filter is changed sequentially until the outputs of the LO and the first filter have the same center frequency.

10. An integrated circuit tuner comprising:

an on-chip crystal having a reference frequency;

means for generating a first oscillator output at the reference frequency;

a first adjustable on-chip filter having a first plurality of selectable capacitors that determine its center frequency;

a second adjustable on-chip filter having a second plurality of selectable capacitors that determine its center frequency;

means for selecting a number of the first plurality of capacitors to adjust the first filter to the reference frequency; and

means for transferring the selection of the first plurality of capacitors to the second plurality of capacitors to adjust the second filter to a frequency proportional to the reference frequency.

11. A method for on-chip filter tuning comprising:

stimulating a dummy filter with a frequency available in the receiver by utilizing the frequency as the filter stimulus;

tuning the dummy filter to its designed center frequency by switching in capacitors to shift the filter response curve down in frequency;

calculating the capacitor values required to center the response of the actual filter to its designed center frequency;

adding the calculated capacitance to the actual filter so that its response curve is centered about its designed center frequency; and

removing the tuning circuitry from the signal path.

12. Electronic tuning circuitry for tuning a filter comprising:

a first switchable capacitor that is part of a tunable filter that is capable of being tuned to a first characteristic frequency;

a dummy filter capable of being tuned to a second characteristic frequency;

a second switchable capacitor that is part of the tunable dummy filter;

a signal generator producing the second characteristic frequency and applying it to the dummy filter;

a first phase detector that compares the phase of the dummy filter input to the dummy filter output;

a comparator that produces an output signal indicative of the dummy filter being tuned to the second characteristic frequency; and

a counter that continues to switch in first and second switchable capacitors simultaneously until disabled by the comparator circuit.

13. The electronic tuning circuitry for tuning a filter of claim 11 further comprising a low pass filter cascaded between the phase detector output and comparator input.

14. The electronic tuning circuitry for tuning a filter of claim 11 further comprising a second phase detector connected in parallel with the first phase detector.

15. The electronic tuning circuitry for tuning a filter of claim 14 in which the second phase detector I and Q inputs are connected to the first phase detector Q and I inputs respectively.

16. The electronic tuning circuitry for tuning a filter of claim 12 in which the circuitry described is configured differentially.

17. The electronic tuning circuitry for tuning a filter of claim 12 in which the first switchable capacitor is selected such that its value is scaled in frequency to the value of the second switchable capacitor to produce the desired tuning response in the filter.

18. Electronic tuning circuitry for tuning a filter comprising:

a dummy filter means for producing a tuned response at a frequency of a locally available frequency generator;

a filter means for filtering unwanted signals from a desired signal;

a phase detector means for detecting a phase difference across a set of dummy filter terminals with minimal DC off set;

a low pass filter means for removing AC signals from the phase detector output;

a comparator means for indicating that a desired phase difference has been achieved; and

a counter means for tuning a filter until disabled by the comparator means.

19. Electronic tuning circuitry for tuning a filter comprising:

a substrate upon which the electronic tuning circuitry is disposed;

a first switchable capacitor that is part of a tunable filter that is capable of being tuned to a first characteristic frequency;

a dummy filter capable of being tuned to a second characteristic frequency;

a second switchable capacitor that is part of the tunable dummy filter;

a signal generator producing the second characteristic frequency and applying it to the dummy filter;

a first phase detector that compares the phase of the dummy filter input to the dummy filter output;

a comparator that produces an output signal indicative of the dummy filter being tuned to the second characteristic frequency; and

a counter that continues to switch in first and second switchable capacitors simultaneously until disabled by the comparator circuit.

20. The electronic tuning circuitry for tuning a filter of claim 19 wherein the substrate is silicon.

21. The electronic tuning circuitry for tuning a filter of claim 19 further comprising a low pass filter cascaded between the phase detector output and comparator input.

22. The electronic tuning circuitry for tuning a filter of claim 19 further comprising a second phase detector connected in parallel with the first phase detector.

23. The electronic tuning circuitry for tuning a filter of claim 22 in which the second phase detector I and Q inputs are connected to the first phase detector Q and I inputs respectively.

24. The electronic tuning circuitry for tuning a filter of claim 19 in which the circuitry described is configured differentially.

25. The electronic tuning circuitry for tuning a filter of claim 19 in which the first switchable capacitor is selected such that its value is scaled in frequency to the value of the second switchable capacitor to produce the desired tuning response in the filter.

Description Submit all comments and votes

FIELD OF THE INVENTION

This application relates generally to receiver circuits and, in particular to a CATV tuner with a frequency plan and architecture that allows the entire receiver, including the filters, to be integrated onto a single integrated circuit.

BACKGROUND OF THE INVENTION

Radio receivers, or tuners, are widely used in applications requiring the reception of electromagnetic energy. Applications can include broadcast receivers such as radio and television, set top boxes for cable television, receivers in local area networks, test and measurement equipment, radar receivers, air traffic control receivers, and microwave communication links among others. Transmission of the electromagnetic energy may be over a transmission line or by electromagnetic radio waves.

The design of a receiver is one of the most complex design tasks in electrical engineering. In the current state of the art, there are many design criteria that must be considered to produce a working radio receiver. Tradeoffs in the design's performance are often utilized to achieve a given objective. There are a multitude of performance characteristics that must be considered in designing the receiver. However, certain performance characteristics are common to all receivers. Distortion and noise are two such parameters. The process of capturing the signal creates distortion that must be accounted for in the design of the radio receiver. Once a radio signal is captured, the noise surrounding the received signal in the receiver must be considered. Radio signals are often extremely weak and if noise is present in the circuit, the signal, even though satisfactorily received, can be easily lost in this noise floor. The current state of the art in receiver design is often directed to overcoming these receiver limitations in a cost effective manner.

SUMMARY OF THE INVENTION

There is therefore provided in a present embodiment of the invention a method for tuning filters. First a dummy filter is stimulated with a frequency that is available locally. Next the dummy filter is tuned to its designed center frequency. This is done by switching in capacitors to shift the filter response curve down in frequency. Next the capacitor values required to center the response of the actual filter to its designed center frequency are determined by using frequency scaling a ratio of the dummy filter's required capacitance to the actual filter's. The required capacitance is added simultaneously with the dummy filter's capacitance. Tuning stops when the dummy filter's response is centered about its tuning frequency. Next the tuning circuitry is disengaged.

Many of the attendant features of this invention will be more readily appreciated as the same becomes better understood by reference to the following detailed description considered in connection with the accompanying drawings, in which like reference symbols designate like parts throughout.

DESCRIPTION OF THE DRAWINGS

These and other features and advantages of the present invention will be better understood from the following detailed description read in light of the accompanying drawings, wherein

FIG. 1 is an illustration of a portion of the over-the-air broadcast spectrum allocations in the United States;

FIG. 2 is an illustration of the frequency spectrum of harmonic distortion products;

FIG. 3 is an illustration of a spectrum of even and odd order intermodulation distortion products;

FIG. 4 is an illustration of interference caused at the IF frequency by a signal present at the image frequency;

FIG. 5 is an illustration of a typical dual conversion receiver utilizing an up conversion and a subsequent down conversion;

Oscillator Figures

FIG. 6 is a semi-schematic simplified timing diagram of differential signals, including a common mode component, as might be developed by a differential crystal oscillator in accordance with the invention;

FIG. 7 is a semi-schematic block diagram of a differential crystal oscillator, including a quartz crystal resonator and oscillator circuit differentially coupled to a linear buffer amplifier in accordance with the invention;

FIG. 8 is a simplified schematic illustration of differential signals present at the output of a crystal resonator;

FIG. 9 is a simplified schematic diagram of a quartz crystal resonator equivalent circuit;

FIG. 10 is a simplified graphical representation of a plot of impedance vs. frequency for a crystal resonator operating near resonance;

FIG. 11 is a simplified graphical representation of a plot of phase vs. frequency for a crystal resonator operating near resonance;

FIG. 12 is a simplified schematic diagram of the differential oscillator circuit of FIG. 7;

FIG. 13 is a simplified, semi-schematic block diagram of a periodic signal generation circuit including a crystal oscillator having balanced differential outputs driving cascaded linear and non-linear buffer stages;

FIG. 14 is a simplified schematic diagram of a differential folded cascade linear amplifier suitable for use in connection with the present invention;

FIG. 15 is a simplified, semi-schematic diagram of a differential nonlinear buffer amplifier suitable for use as a clock buffer in accordance with the invention;

FIG. 16 is a semi-schematic illustration of an alternative embodiment of the differential oscillator driver circuit;

FIG. 17 is an block diagram of a differential crystal oscillator as a reference signal generator in a phase-lock-loop; and

FIG. 18 is a simplified block diagram of an illustrative frequency synthesizer that might incorporate the differential periodic signal generation circuit of the invention.

Coarse/Fine PLL Tuning Figures

FIG. 19 is a block diagram illustrating the exemplary frequency conversions for receiver tuning utilized in the embodiments of the invention;

FIG. 20 is a block diagram of an exemplary tuner designed to receive a 50 to 860 MHz bandwidth containing a multiplicity of channels;

FIG. 21 is an exemplary table of frequencies utilizing coarse and fine PLL tuning to derive a 44 MHz IF;

FIG. 22 is an illustration of an alternative embodiment of the coarse and fine PLL tuning method to produce an exemplary final IF of 36 MHz;

FIG. 23 is a block diagram of a dummy component used to model an operative component on an integrated circuit chip;

Filter Tuning Figures

FIG. 24a is a block diagram of a tuning process;

FIG. 24b is a flow diagram of the tuning process;

FIG. 24c is an exemplary illustration of the tuning process;

FIG. 25 is a block diagram of an exemplary tuning circuit;

FIG. 26 illustrates the amplitude and phase relationship in an LC filter at resonance;

FIG. 27 is a schematic diagram showing the configuration of switchable capacitors in a differential signal transmission embodiment;

Inductor Q Temperature Compensation Figures

FIG. 28 is an illustration of a typical spiral inductor suitable for integrated circuit applications;

FIG. 29 is an illustration of the effect of decreasing "Q" on the selectivity of a tuned circuit;

FIG. 30 is an illustration of a typical filter bank utilized in embodiments of the invention for filtering I and Q IF signals;

FIG. 31 is a diagram of a transconductance stage with an LC load;

FIG. 32 shows a transconductance stage with an LC load and Q enhancement;

FIG. 33 shows a method of tuning inductor Q over temperature;

Communications Receiver Figures

FIG. 34 is a block diagram of a communications network utilizing a receiver according to any one of the exemplary embodiments of the invention;

Receiver Front End-Programable Attenuator and LNA Figures

FIG. 35 is an is an illustration of the input and output signals of the integrated switchless programmable attenuator and low noise amplifier;

FIG. 36 is a functional block diagram of the integrated switchless programmable attenuator and low noise amplifier circuit;

FIG. 37 is a simplified diagram showing the connection of multiple attenuator sections to the output of the integrated switchless programmable attenuator and low noise amplifier;

FIG. 38 is an illustration of an exemplary embodiment showing how the attenuator can be removed from the circuit so that only the LNAs are connected;

FIG. 39 is an attenuator circuit used to achieve one dB per step attenuation;

FIG. 40 is an exemplary embodiment of an attenuator for achieving a finer resolution in attenuation then shown in FIG. 5;

FIG. 41 is an illustration of the construction of series and parallel resistors used in the attenuator circuit of the integrated switchless programmable attenuator and low noise amplifier;

FIG. 42 is an illustration of a preferred embodiment utilized to turn on current tails of the differential amplifiers;

FIG. 43 is an illustration of an embodiment showing how the individual control signals used to turn on individual differential pair amplifiers are generated from a single control signal;

FIGS. 44a and 44b are illustrations of an embodiment of comparator circuitry used to activate individual LNA amplifier stages;

Local Oscillator Generation Figures

FIG. 45 is a block diagram illustrating the exemplary generation of the local oscillator signals utilized in the embodiments of the invention;

Narrow Band VCO Tuning Figures

FIG. 46 is a schematic of a PLL having its VCO controlled by an embodiment of a VCO tuning control circuit;

FIG. 47 is a process flow diagram illustrating the process of tuning the VCO with an embodiment of a VCO control circuit;

Receiver Figures

FIG. 48 is a block diagram of the first exemplary embodiment of the invention;

FIG. 49 is an illustration of the frequency planning utilized in the exemplary embodiments of the invention;

FIG. 50 is a block diagram showing how image frequency cancellation is achieved in an I/Q mixer;

FIG. 51 is a block diagram of the second exemplary embodiment of the present invention;

FIG. 52 is a block diagram of the third exemplary embodiment of the present invention;

FIG. 53 is a block diagram of a CATV tuner that incorporates the fully integrated tuner architecture; and

Telephony Over Cable Embodiment Figure

FIG. 54 is a block diagram of a low power embodiment of the receiver that has been configured to receive cable telephony signals.

Electronic Circuits Incorporation Embodiments of the Receiver Figures

FIG. 55 is a block diagram of a set top box that incorporates the receiver embodiments;

FIG. 56 is a block diagram of a television that incorporates the receiver embodiments;

FIG. 57 is a block diagram of a VCR that incorporates the receiver embodiments; and

FIG. 58 is a block diagram of a cable modem that incorporates the integrated switchless programmable attenuator and low noise amplifier.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is an illustration of a portion of the radio frequency spectrum allocations by the FCC. Transmission over a given media occurs at any one of a given range of frequencies that are suitable for transmission through a medium. A set of frequencies available for transmission over a medium are divided into frequency bands 102. Frequency bands are typically allocations of frequencies for certain types of transmission. For example FM radio broadcasts, FM being a type of modulation, is broadcast on the band of frequencies from 88 MHz to 108 MHz 104. Amplitude modulation (AM), another type of modulation, is allocated the frequency band of 540 kHz to 1,600 kHz 106. The frequency band for a type of transmission is typically subdivided into a number of channels. A channel 112 is a convenient way to refer to a range of frequencies allocated to a single broadcast station. A station broadcasting on a given channel may transmit one or more radio frequency (RF) signals within this band to convey the information of a broadcast. Thus, several frequencies transmitting within a given band may be used to convey information from a transmitter to a broadcast receiver. For example, a television broadcast channel broadcasts its audio signal(s) 108 on a frequency modulated (FM) carrier signal within the given channel. A TV picture (P) 110 is a separate signal broadcast using a type of amplitude modulation (AM) called vestigial side band modulation (VSB), and is transmitted within this channel.

In FIG. 1 channel allocations for a television broadcast band showing the locations of a picture and a sound carrier frequencies within a channel are shown. Each channel 112 for television has an allocated fixed bandwidth of 6 MHz. The picture 110 and sound 108 carriers are assigned a fixed position relative to each other within the 6 MHz band. This positioning is not a random selection. The picture and sound carriers each require a predetermined range of frequencies, or a bandwidth (BW) to sufficiently transmit the desired information. Thus, a channel width is a fixed 6 MHz, with the picture and sound carrier position fixed within that 6 MHz band, and each carrier is allocated a certain bandwidth to transmit its signal.

In FIG. 1 it is seen that there are gaps between channels 114, and also between carrier signals 116. It is necessary to leave gaps of unused frequencies between the carriers and between the channels to prevent interference between channels and between carriers within a given channel. This interference primarily arises in the receiver circuit that is used to receive these radio frequency signals, convert them to a usable frequency, and subsequently demodulate them.

Providing a signal spacing allows the practical design and implementation of a receiver without placing unrealistic requirements on the components in the receiver. The spaces help prevent fluctuations in the transmission frequency or spurious responses that are unwanted byproducts of the transmission not to cause interference and signal degradation within the receiver. Also, signal spacing allows the design requirements of frequency selective circuits in the receiver to be relaxed, so that the receiver may be built economically while still providing satisfactory performance. These spectrum allocations and spacings were primarily formulated when the state of the art in receiver design consisted of discrete components spaced relatively far apart on a printed circuit board. The increasing trend towards miniaturization has challenged these earlier assumptions. The state of the art in integrated circuit receiver design has advanced such that satisfactory performance must be achieved in light of the existing spectrum allocations and circuit component crowding on the integrated circuit. New ways of applying existing technology, as well as new technology are continually being applied to realize a miniaturized integrated receiver that provides satisfactory performance. Selectivity is a principal measure of receiver performance. Designing for sufficient selectivity not only involves rejecting other channels, but the rejection of distortion products that are created in the receiver or are part of the received signal. Design for minimization or elimination of spurious responses is a major objective in state of the art receiver design.

FIG. 2 is an illustration of harmonic distortion products. Transmitted spurious signals, and spurious signals generated in a receiver, most commonly consist of harmonics created by one frequency and intermodulation distortion, created by the interaction of multiple frequencies. Spurious signals at other than the desired frequency arise from the inherent nonlinear properties in the circuit components used. These nonlinearities can not be eliminated, but by careful engineering the circuitry can be designed to operate in a substantially linear fashion.

When a single frequency called a fundamental 202 is generated, unwanted spurious signals 204 are always generated with this fundamental. The spurious signals produced as a result of generating a single frequency (f) 202 are called harmonics 204 and occur at integer multiples of the fundamental frequency (2f, 3f, . . . ) The signal strength or amplitude of these harmonics decrease with increasing harmonic frequency. Fortunately these distortion products fall one or more octaves away from the desired signal, and can usually be satisfactorily filtered out with a low pass filter that blocks all frequencies above a pre-selected cut-off frequency. However, if the receiver is a wide band or multi octave bandwidth receiver, these harmonics will fall within the bandwidth of the receiver and cannot be low pass filtered, without also filtering out some of the desired signals. In this case, other methods known to those skilled in the art, such as reducing the distortion products produced, must be used to eliminate this distortion.

Radio signals do not exist in isolation. The radio frequency spectrum is populated by many channels within a given band transmitting at various frequencies. When a radio circuit is presented with two or more frequencies, these frequencies interact, or intermodulate, to create distortion products that occur at known frequency locations.

FIG. 3 is an illustration of intermodulation distortion products. Whenever two or more frequencies are present they interact to produce additional spurious signals that are undesired. FIG. 3 illustrates a spurious response produced from the interaction of two signals, f.sub.1 302 and f.sub.2 304. This particular type of distortion is called intermodulation distortion (IMD). These intermodulation distortion products 306 are assigned orders, as illustrated. In classifying the distortion the IM products are grouped into two families, even and odd order IM products. Odd order products are shown in FIG. 3.

In a narrow band systems the even order IM products can be easily filtered out, like harmonics, because they occur far from the two original frequencies. The odd order IM products 306 fall close to the two original frequencies 302, 304. In a receiver these frequencies would be two received signals or a received channel and a local oscillator. These products are difficult to remove. The third order products 306 are the most problematic in receiver design because they are typically the strongest, and fall close within a receiver's tuning band close to the desired signal. IM distortion performance specifications are important because they are a measure of the receiver's immunity to strong out of band signal interference.

Third order products 308 occur at (f.sub.1 -.DELTA.f) and at (f.sub.2 +.DELTA.f), where .DELTA.f=f.sub.2 -f.sub.1. These unwanted signals may be generated in a transmitter and transmitted along with desired signal or are created in a receiver. Circuitry in the receiver is required to block these signals. These unwanted spurious responses arise from nonlinearities in the circuitry that makes up the receiver.

The circuits that make up the receiver though nonlinear are capable of operating linearly if the signals presented to the receiver circuits are confined to signal levels within a range that does not call for operation of the circuitry in the nonlinear region. This can be achieved by careful design of the receiver.

For example, if an amplifier is over driven by signals presented to it greater than it was designed to amplify, the output signal will be distorted. In an audio amplifier this distortion is heard on a speaker. In a radio receiver the distortion produced in nonlinear circuits, including amplifiers and mixers similarly causes degradation of the signal output of the receiver. On a spectrum analyzer this distortion can be seen; levels of the distortion increase to levels comparable to the desired signal.

While unwanted distortion such as harmonic distortion, can be filtered out because the harmonics most often fall outside of the frequency band received, other distortion such as inter-modulation distortion is more problematic. This distortion falls within a received signal band and cannot be easily filtered out without blocking other desired signals. Thus, frequency planning is often used to control the location of distortion signals that degrade selectivity.

Frequency planning is the selection of local oscillator signals that create the intermediate frequency (IF) signals of the down conversion process. It is an analytical assessment of the frequencies being used and the distortion products associated with these frequencies that have been selected. By evaluating the distortion and its strength, an engineer can select local oscillator and IF frequencies that will yield the best overall receiver performance, such as selectivity and image response. In designing a radio receiver, the primary problems encountered are designing for sufficient sensitivity, selectivity and image response.

Selectivity is a measure of a radio receiver's ability to reject signals outside of the band being tuned by a radio receiver. A way to increase selectivity is to provide a resonant circuit after an antenna and before the receiver's frequency conversion circuitry in a "front end." For example, a parallel resonant circuit after an antenna and before a first mixer that can be tuned to the band desired will produce a high impedance to ground at the center of the band. The high impedance will allow the antenna signal to develop a voltage across this impedance. Signals out of band will not develop the high voltage and are thus attenuated.

The out of band signal rejection is determined by a quality factor or "Q" of components used in the resonant circuit. The higher the Q of a circuit in the preselector, the steeper the slope of the impedance curve that is characteristic of the preselector will be. A steep curve will develop a higher voltage at resonance for signals in band compared to signals out of band. For a resonant circuit with low Q a voltage developed across the resonant circuit at a tuned frequency band will be closer in value to the voltage developed across the resonant circuit out of band. Thus, an out of band signals would be closer in amplitude to an in band signals than if a high Q circuit were constructed.

This type of resonant circuit used as a preselector will increase frequency selectivity of a receiver that has been designed with this stage at its input. If an active preselector circuit is used between an antenna and frequency conversion stages, the sensitivity of the receiver will be increased as well as improving selectivity. If a signal is weak its level will be close to a background noise level that is present on an antenna in addition to a signal. If this signal cannot be separated from the noise, the radio signal will not be able to be converted to a signal usable by the receiver. Within the receiver's signal processing chain, the signal's amplitude is decreased by losses at every stage of the processing. To make up for this loss the signal can be amplified initially before it is processed. Thus, it can be seen why it is desirable to provide a circuit in the receiver that provides frequency selectivity and gain early in the signal processing chain.

Radio frequency tuners are increasingly being designed with major portions of their circuitry implemented as an integrated circuit. In the state of the art to minimize distortion products created in the receiver, exotic materials such as gallium arsenide (GaAs) are used. A receiver implemented on this type of material will typically have lower distortion and noise present than in a similarly constructed receiver constructed on silicon. Silicon, is an attractive material due to its low cost. In addition, a CMOS circuit implemented on silicon has the additional benefit of having known processing characteristics that allow a high degree of repeatability from lot to lot of wafers. The state of the art has not achieved a completely integrated receiver in CMOS circuitry. A reason for this is the difficulty of eliminating receiver distortion and noise.

The distortion products discussed above that are created in the receiver can, in the majority of cases, also be reduced by setting an appropriate drive level in the receiver, and by allowing a sufficient spacing between carriers and channels. These receiver design parameters are dependent upon many other factors as well, such as noise present in the system, frequency, type of modulation, and signal strength among others. Noise is one of the most important of these other parameters that determines the sensitivity of the receiver, or how well a weak signal may be satisfactorily received.

Noise is present with the transmitted signal, and also generated within a receiver. If excessive noise is created in a receiver a weak signal may be lost in a "noise floor". This means that the strength of the received signal is comparable to the strength of the noise present, and the receiver is incapable of satisfactorily separating a signal out of this background noise, or floor. To obtain satisfactory performance a "noise floor" is best reduced early in a receiver's chain of circuit components.

Once a signal is acquired and presented to a receiver, in particularly an integrated receiver with external pins, additional noise may be radiated onto those pins. Thus, additional added noise at the receiver pins can degrade the received signal.

In addition to the noise that is present on an antenna or a cable input to a receiver, noise is generated inside the radio receiver. At a UHF frequency range this internal noise predominates over the noise received with the signal of interest. Thus, for the higher frequencies the weakest signal that can be detected is determined by the noise level in the receiver. To increase the sensitivity of the receiver a "pre-amplifier" is often used after an antenna as a receiver front end to boost the signal level that goes into the receiver. This kind of pre-amplification at the front end of the amplifier will add noise to the receiver due to the noise that is generated inside of this amplifier circuit. However, the noise contribution of this amplifier can be minimized by using an amplifier that is designed to produce minimal noise when it amplifies a signal, such as an LNA. Noise does not simply add from stage to stage; the internal noise of the first amplifier substantially sets the noise floor for the entire receiver.

In calculating a gain in a series of cascaded amplifiers the overall gain is simply the sum of the gains of the individual amplifiers in decibels. For example, the total gain in a series of two amplifiers each having a gain of 10 dB is 20 dB for a overall amplifier. Noise floor is commonly indicated by the noise figure (NF). The larger the NF the higher the noise floor of the circuit.

A Cascaded noise figure is not as easily calculated as amplifier gain; its calculation is non-intuitive. In a series of cascaded amplifiers, gain does not depend upon the positioning of the amplifiers in the chain. However, in achieving a given noise