A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
This application is a continuation of Ser. No. 09/357,374 filed Jul. 20, 1999 now U.S. Pat. No. 6,097,404, which is a continuation of Ser. No. 08/940,632 filed Sep. 30, 1997 now U.S. Pat. No. 5,999,197, which is a division of Ser. No. 08/317,130 filed Oct. 3, 1994, now U.S. Pat. No. 5,713,011.
Priority Data
Oct 15, 1993 [JP] 5-258040 Oct 15, 1993 [JP] 5-281865 Aug 10, 1994 [JP] 6-209176
In a semiconductor memory device equipped with a memory cell array in which dynamic memory cells are arrayed, for example, in a matrix, a technique speeds up of a read operation. In the read cycle, an external access controller outputs an external access execution timing signal which changes to active after the change of the output enable signal to active, and changes to inactive after a start of the latch of the read signal caused by changes of the latch signal to active and inactive. In the read cycle, the refresh controller outputs the refresh execution timing signal which changes to active according to the change of the latch signal to active while the refresh requirement signal is active, and stays active for a predetermined time period.
A segment terminal is structured to function as a data input terminal and a data output terminal in a manner that they can be switched from one to the other, and a memory cell formed from a two-port memory is provided with a port, through which data stored in the memory is read and outputted to the segment terminal, that is structured to function as a port for reading stored data and writing data. In a test mode, test data is supplied to the segment terminal, and the test data is written in the memory cell through the port through which data stored in the memory is read and outputted to the segment terminal. The segment terminal is provided for each of the columns or rows of a dot matrix. Test data is written in the memory cells in each of the columns or rows through switching the memory cells in which the test data is to be written. As a result, the test data is written in the memory cells in the unit of the number of the segment terminals, and therefore, the time for writing the test data is shortened.
