A circuit arrangement as part of a shift register is proposed for controlling switch elements arranged in the form of a chain or a matrix, including four clock signals that are phase shifted by 90.degree. with respect to one another for the control, with at least one transistor switching through a signal that is independent of the shift clock signals to the output to control the switch elements depending on the information to be shifted.
A shift register having a built-in level shifter includes a buffer outputting a shift pulse using a first clock signal and a first supply voltage via voltages at first and second nodes; a first controller controlling the voltage of the first node via the start pulse and the second node; and a second controller controlling the second node voltage using the first and second supply voltage via the start pulse and the second clock signal. The level shifter includes a third controller forming a current path between third supply voltage input line and first supply voltage input line controlling a third node using the first supply voltage and a third supply voltage via the voltage of the second node and two of first to fourth clock signals; and an output part outputting the level-shifted shift pulse using the first and third supply voltage via the voltage at the third node.
