Semiconductor test interconnect with variable flexure contacts

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FIELD OF THE INVENTION

This invention relates generally to semiconductor testing, and specifically to an improved interconnect for electrically testing semiconductor components such as dice, packages, wafers, panels, boards, and electronic assemblies containing dice or packages.

BACKGROUND OF THE INVENTION

Semiconductor components, such as bare dice, chip scale packages, BGA devices and wafers can include terminal contacts in the form of bumped contacts. This type of component is sometimes referred to as a "bumped" component (e.g., bumped die, bumped wafer). The bumped contacts provide a high input/output capability for a component, and permit the component to be surface mounted, or alternately flip chip mounted, to a mating substrate, such as a printed circuit board (PCB). Typically, the bumped contacts comprise solder bumps or balls, which permit the components to be bonded to the mating substrate using a solder reflow process. For some components, such as chip scale packages and BGA devices, the bumped contacts can be arranged in a dense array, such as a ball grid array (BGA), or a fine ball grid array (FBGA).

Rather than bumped contacts, semiconductor components can also include terminal contacts in the form of pin contacts, or spring contacts. For example, U.S. Pat. No. 5,496,667 to Farnworth et al. discloses pin contacts, and spring contacts, on unpackaged semiconductor dice.

For performing test procedures on semiconductor components temporary electrical connections must be made with the terminal contacts. Different types of interconnects have been developed for making these temporary electrical connections. For example, a wafer probe card is one type of interconnect that is used to test semiconductor wafers. Another type of interconnect, is contained within a carrier for temporarily packaging singulated components, such as bare dice and chip scale packages, for test and burn-in. In either case, the interconnects include interconnect contacts that make the temporary electrical connections with the terminal contacts on the components.

One problem with making these temporary electrical connections is that variations can occur in the planarity, size, and location of the terminal contacts on the components. For example, the planarity of bumped contacts can vary due to variations in height and diameter of the bumps. Similarly, pin contacts or spring contacts can have different heights and diameters. These variations can occur between the terminal contacts on the same component, and between the terminal contacts on different components. It is advantageous for an interconnect to be able to accommodate these variations, particularly variations in the height and planarity of the terminal contacts. This problem is compounded because the interconnect contacts must penetrate native oxide layers on the terminal contacts to make low resistance electrical connections.

The present invention is directed to an interconnect for making temporary electrical connections with semiconductor components having terminal contacts in the form of bumps, pins or springs.

SUMMARY OF THE INVENTION

In accordance with the present invention, an improved interconnect for testing semiconductor components is provided. Also provided, are a test system incorporating the interconnect, a method for fabricating the interconnect, and a testing method employing the interconnect.

The interconnect includes a substrate, and a plurality of interconnect contacts on the substrate configured to electrically engage terminal contacts on the components, such as bumped contacts, pin contacts or spring contacts. Several different embodiments of the interconnect contacts are provided including: metallized recesses sized and shaped to retain the terminal contacts; metallized penetrating projections configured to penetrate the terminal contacts; metallized recesses with penetrating projections; and metal leads on polymer tape cantilevered over metallized recesses.

The interconnect also includes one or more cavities in the substrate configured to form flexible segments of the substrate, that allow the interconnect contacts to flex, and to move independently of one another, to accommodate variations in the size, location and planarity of the terminal contacts. A location and size of the cavities can be selected to form the flexible segments, with a desired compliancy, or spring constant. In addition, the cavities can be in flow communication with a pressurized fluid or gas source, such that a flexure of the interconnect contacts can be adjusted as required, for a particular testing application. Also, the pressurized cavities permit a variable backside biasing force to be exerted on the flexible segments, to counteract a biasing force applied from a front side of the interconnect by a testing apparatus such as a wafer prober or test carrier. Alternately, the cavities can be filled with an elastomeric material, selected to provide a desired compliancy, or spring constant, for the flexible segments and the substrate.

In a first embodiment the cavities comprise separate pockets, aligned with individual interconnect contacts. In a second embodiment the cavities comprise elongated grooves aligned with multiple interconnect contacts. In a third embodiment the cavity comprises a single pocket large enough to encompass a periphery of multiple interconnect contacts.

The interconnect can be configured for die level testing of discrete components, such as bare dice or chip scale packages, or alternately for wafer level testing of multiple components contained on a common substrate, such as a wafer, a panel, a circuit board, or an electronic assembly. For a die level test system, the interconnect is configured for assembly in a testing apparatus, such as a carrier, configured to retain one or more components in electrical communication with testing circuitry. The testing apparatus includes a base on which the interconnect is mounted, and a force applying mechanism for biasing the components against the interconnect. For a wafer level test system, the interconnect is configured for use with a wafer testing apparatus, such as a wafer prober, or a wafer level burn-in system. In an illustrative wafer level test system the interconnect replaces a conventional probe card.

In an illustrative fabrication method, the interconnect comprises an etchable material such as silicon or ceramic, such that etching and metallization processes can be used to fabricate the interconnect contacts and cavities. Alternately the interconnect can comprise plastic, such that micro-molding and metallization processes can be used to fabricate the interconnect contacts and cavities.

The test method includes the steps of: providing the interconnect, electrically engaging the component using the interconnect, and then allowing the interconnect contacts to move