A method for adjusting a phase of a sampling frequency of ADC is disclosed. The method includes converting an analog signal into a first digital signal according to a first phase of the sampling frequency during a first time interval; calculating a first value according to the first digital signal; converting the analog signal into a second digital signal according to a second phase of the sampling frequency during a second time interval; calculating a second value according to the second digital signal; and adjusting the phase of the sampling frequency according to the first value and the second value.

In a method and device for reconstructing and controlling the phase position of a sample clock relative to an analog signal to be sampled, the analog signal is sampled at a plurality of different instants in time during a time interval and a plurality of time gradients at the same or different instants in time are determined. The original analog signal is reconstructed, at least in segments, based on the sampled values and determined time gradients. The reconstructed signal curve is utilized to determine the phase position of the sampling clock relative to the analog signal. This phase position is provided to a control loop which readjusts the phase position of the sampling clock accordingly.

The invention relates to a method and a device for matching the phase between the pixel clock of a graphics card and the sampling clock of a flat-panel display with an analog interface in a system comprising flat-panel display, graphics card and computer. Herein the rising edge of a video pulse of a sufficiently bright image spot in the first image column close to the back-porch region is determined. The falling edge of a video pulse at a sufficiently bright image spot in the last image column close to the front-porch region is determined, and the phase is adjusted such that the sampling instant is situated approximately at the midpoint between the rising and falling edges of a video pulse.

A system for converting analog video signals to digital video signals receives an analog video signal that generates a reference horizontal synchronization signal. A phase-locked loop receives the reference horizontal synchronization signal and generates a pixel clock signal and a horizontal synchronization signal from the reference horizontal synchronization signal. An analog-to-digital converter converts the analog video signals to digital video signals. Differences between the measured values of the sampling of a test line of adjacent pixels are formed and phase parameters of the different phase positions are generated by summation of these differences. A phase position of the video signal from the phase parameters is determined, and the phase position is determined with the set phase position, and based on the comparison the set phase is changed.

A network receiver is configured for receiving a modulated carrier signal representing a data frame from another network transceiver via a network medium, the modulated carrier signal may be either a pulse position modulated (PPM) carrier, a quadrature amplitude modulated (QAM) carrier, or a compatibility mode frame including both PPM and QAM portions. The network receiver is configured to select an A/D sampling clock frequency corresponding to the detected frame type.