An NMOS field effect transistor may be utilized to drive the memory cell of a phase change memory. As a result, the leakage current may be reduced dramatically.

In a semiconductor memory device having a crosspoint-type memory cell array, each reference level between two adjacent memory levels when memory levels of multi-level information stored in a memory cell are arranged in order of size of resistance values of a corresponding variable resistive element is defined by a reference current in a middle state between a first and a second current states. In the first current state, a readout current of high resistance selected cell in which the resistance is higher in the two adjacent memory levels becomes the largest state depending on a distribution pattern of a resistance state of the other unselected cell. In the second current state, a readout current of low resistance selected cell in which the resistance is lower in the two adjacent memory levels becomes a smallest state depending on a distribution pattern of a resistance state of the other unselected memory cell.

Provided are a phase-change memory device and method that maintains a resistance of a phase-change material in a reset state within a constant resistance range. In the method, data is provided to a first phase-change memory cell and then it is first determined whether data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are not identical, a complementary write current is provided to the first phase-change memory cell and it is second determined whether the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical. If the data stored in the first phase-change memory cell and the data provided to the first phase-change memory cell are identical, data is provided to a second phase-change memory cell.

Output signals of two adjacent data signal lines DA1 to DAn and DB1 to DBn are supplied to comparators CMP1 to CMPn, respectively. When pixels are inspected, different signal potentials are input to signal input terminals 14a and 14b. Signals are written to pixels from the first row to the last row. Thereafter, a pre-charging process is performed by supplying a voltage to the terminals 14a and 14b. Thereafter, signals are read from all the pixels from the first row to the last row. The signal potentials that have been read are compared by the comparators CMP1 to CMPn. Depending on the relations of voltages written as digitally-compared outputs of the comparators CMP1 to CMPn, defective pixels are detected.

A memory circuit comprising a memory cell which has a resistance memory element and is connected between a ground terminal and a capacitor has a reference memory cell with a reference resistor which is connected between the ground terminal and a reference capacitor, in which case, during the reading operation of the memory cell, the memory cell and the reference memory cell are switched on in order to charge or discharge the capacitor and the reference capacitor, and an evaluation device evaluates the difference between the electrical potentials of the capacitor and the reference capacitor at a predetermined instant after the switching-on of the memory cell and the reference memory cell.