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| United States Patent | 6320201 |
| Link to this page | http://www.wikipatents.com/6320201.html |
| Inventor(s) | Corbett; Tim J. (Boise, ID);
Scholer; Raymond P. (Boise, ID);
Gonzalez; Fernando (Boise, ID) |
| Abstract | A semiconductor test chip including a plurality of test functions. The test
functions of the semiconductor test chip include bond pad pitch and size
effects on chip design, wire bond placement accuracy regarding placement
of the wire bond on the bond pad, evaluation of bond pad damage
(cratering) effect on the area of the chip below the bond pad during
bonding of the wire on the bond pad, street width effects regarding the
use of thinner saw cuts in cutting the individual chips from the wafer,
thermal impedance effects for thermal testing capabilities, ion mobility
evaluation capabilities and chip on board in flip chip application test
capabilities. |
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Title Information  |
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Drawing from US Patent 6320201 |
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Semiconductor reliability test chip |
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| Publication Date |
November 20, 2001 |
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| Filing Date |
July 20, 2000 |
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| Parent Case |
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation of application Ser. No. 09/298,300,
filed Apr. 23, 1999, now U.S. Pat. 6,157,046, issued Dec. 5, 2000, which
is a continuation of application Ser. No. 08/916,114, filed Aug. 21, 1997,
now U.S. Pat. 5,936,269, issued Aug. 10, 1999, which is a continuation of
application Ser. No. 08/560,544, filed Nov. 17, 1995, now U.S. Pat.
5,751,015, issued May 12, 1998. |
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Title Information |
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References |
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Public's "Guesstimation" of Royalty Value
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Market Review |
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Technical Review |
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Claims |
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What is claimed is:
1. A semiconductor test chip having a plurality of test functions
comprising:
a semiconductor chip including a periphery having at least four sides, a
plurality of contact pads located substantially adjacent at least a
portion of at least one side of the periphery of the semiconductor chip,
at least a portion of the plurality of contact pads being located in a
first row and a second row located substantially adjacent behind the first
row on at least a portion of at least one side of the semiconductor chip
and at least a portion of one conductive line located substantially in a
scribe area extending about at least a portion of the periphery of the
semiconductor chip.
2. The semiconductor test chip of claim 1, wherein the plurality of contact
pads is located in at least two rows substantially adjacent the periphery
of the semiconductor chip on a portion of a periphery of at least a first
side and a second of the semiconductor chip.
3. The semiconductor test chip of claim 1, wherein the plurality of contact
pads is of at least two different geometric shapes.
4. The semiconductor test chip of claim 1, wherein at least two of the
contact pads of the plurality of contact pads differ in size.
5. The semiconductor test chip of claim 1, wherein the plurality of contact
pads includes contact pads having different pitches of mounting on the
semiconductor chip.
6. The semiconductor test chip of claim 1, wherein the semiconductor test
chip further includes:
a plurality of conductive lines located substantially in the scribe area of
the semiconductor chip extending substantially throughout the periphery of
the semiconductor chip.
7. The semiconductor test chip of claim 1, wherein the semiconductor test
chip further includes:
a plurality of conductive lines located substantially in the scribe area of
the semiconductor chip extending throughout a portion of the periphery of
the semiconductor chip, at least two lines of the plurality of conductive
lines having a width which differs from one another.
8. The semiconductor test chip of claim 1, wherein the semiconductor test
chip further includes:
a plurality of conductive lines located substantially in the scribe area of
the semiconductor chip extending throughout a portion of the periphery of
the semiconductor chip, each line of the plurality of conductive lines
having a spacing which differs from another line of the plurality of
conductive lines.
9. The semiconductor test chip of claim 1, wherein the plurality of contact
pads is formed in a plurality of groups of contact pads, each group of
contact pads extending substantially about one side of the periphery of
the semiconductor chip.
10. The semiconductor test chip of claim 1, wherein the plurality of
contact pads is formed in a plurality of groups of contact pads extending
substantially about the periphery of the semiconductor chip, each
individual group of contact pads being of different size than another
group of contact pads of the plurality of contact pads.
11. The semiconductor test chip of claim 1, wherein the plurality of
contact pads is formed in a plurality of groups of contact pads extending
substantially about the portion of the periphery of the semiconductor
chip, each group of the plurality of groups of contact pads including at
least a first row of contact pads and at least a second row of contact
pads located adjacent the first row of contact pads.
12. The semiconductor test chip of claim 1, wherein the semiconductor chip
further includes:
a polysilicon area located under a portion of the plurality of contact
pads.
13. The semiconductor test chip of claim 1, wherein the semiconductor chip
further includes:
an area of polysilicon located under a portion of the plurality of contact
pads, the area of polysilicon having at elast two differing
configurations.
14. The semiconductor test chip of claim 1, wherein the semiconductor chip
further includes:
a plurality of resistive type heaters located on a portion of the
semiconductor chip.
15. The semiconductor test chip of claim 14, wherein each resistive type
heater of the plurality of resistive type heaters is independently
connected to a connector pad on the semiconductor chip.
16. The semiconductor test chip of claim 1, wherein the semiconductor test
chip further includes:
a plurality of transistors to measure any temperature gradient in the
semiconductor chip.
17. The semiconductor test chip of claim 1, wherein the semiconductor test
chip further includes:
a plurality of thin gate and thick gate transistor devices for measurement
of temperature or ion contamination of the semiconductor chip.
18. The semiconductor test chip of claim 1, wherein the semiconductor test
chip further includes:
a plurality of resistors for measurement of thermal performance of a
portion of the semiconductor chip and any package in which it is mounted.
19. The semiconductor test chip of claim 1, wherein the semiconductor chip
is substantially square in shape.
20. The semiconductor test chip of claim 1, wherein the semiconductor test
chip further includes:
a plurality of flip chip test pads located substantially in a center
portion of the semiconductor chip.
21. The semiconductor test chip of claim 1, wherein the semiconductor test
chip further includes:
a plurality of flip chip test pads in an array located in substantially a
center portion of the semiconductor chip.
22. The semiconductor test chip of claim 1, wherein the semiconductor test
chip further includes:
a plurality of flip chip test pads located in substantially a center of the
semiconductor chip, a portion of the plurality of flip chip test pads
being connected in a daisy chain connection by conductors extending
therebetween, the portion of the plurality of flip chip test pads being
connected in the daisy chain being independent of other flip chip test
pads of the plurality of flip chip test pads.
23. A semiconductor test chip having a plurality of test functions
comprising:
a semiconductor chip including a periphery formed by a plurality of sides,
a plurality of contact pads located substantially adjacent a portion of
the periphery of the semiconductor chip, the plurality of contact pads
forming a plurality of groups of contact pads extending substantially
about at least a portion of at least one side the periphery of the
semiconductor chip, each group of the plurality of groups of contact pads
including at least a first row of contact pads and at least a second row
of contact pads located adjacent the first row of contact pads, a portion
of the plurality of contact pads including active circuitry of the
semiconductor chip.
24. The semiconductor test chip of claim 23, wherein the plurality of
contact pads is located in at least two rows substantially adjacent the
periphery of the semiconductor chip on a portion of a periphery of at
least one side of the semiconductor chip.
25. The semiconductor test chip of claim 23, wherein the plurality of
contact pads is of at least two different geometric shapes.
26. The semiconductor test chip of claim 23, wherein at least two of the
contact pads of the plurality of contact pads differ in size.
27. The semiconductor test chip of claim 23, wherein the plurality of
contact pads includes contact pads having different pitches of mounting on
the semiconductor. chip.
28. The semiconductor test chip of claim 23, wherein the semiconductor test
chip further includes:
at least one line located substantially in a scribe area of the chip
extending about a portion of the periphery of the semiconductor chip.
29. The semiconductor test chip of claim 23, wherein the semiconductor test
chip further includes:
a plurality of lines located substantially in a scribe of the chip
extending substantially throughout the periphery of the semiconductor
chip.
30. The semiconductor test chip of claim 23, wherein the semiconductor test
chip further includes:
a plurality of lines located substantially in a scribe area of the
semiconductor chip extending throughout a portion of the periphery of the
semiconductor chip, at least two lines of the plurality of lines having a
width which differs from another line of the plurality of lines.
31. The semiconductor test chip of claim 23, wherein the semiconductor test
chip further includes:
a plurality of lines located substantially in a scribe area of the
semiconductor chip extending throughout a portion of the periphery of the
semiconductor chip, each line of the plurality of lines having a spacing
which differs from another line of the plurality of lines.
32. The semiconductor test chip of claim 23, wherein the plurality of
contact pads is formed in a plurality of groups of contact pads, each
group of contact pads extending substantially about one side of the
periphery of the semiconductor chip.
33. The semiconductor test chip of claim 23, wherein the plurality of
contact pads formed in a plurality of groups of contact pads extends
substantially about the periphery of the semiconductor chip, each
individual group of contact pads being of a different size than another
group of contact pads of the plurality of contact pads.
34. The semiconductor test chip of claim 23, wherein the semiconductor chip
further includes:
a polysilicon area located under at least a portion of the plurality of
contact pads.
35. The semiconductor test chip of claim 23, wherein the semiconductor chip
further includes:
an area of polysilicon located under a portion of the plurality of contact
pads, the area of polysilicon having at least two differing
configurations.
36. The semiconductor test chip of claim 23, wherein the semiconductor chip
further includes:
a plurality of resistive type heaters located on a portion of the
semiconductor chip.
37. The semiconductor test chip of claim 36, wherein each resistive type
heater of the plurality of resistive type heaters is independently
connected to a connector pad on the semiconductor chip.
38. The semiconductor test chip of claim 23, wherein the semiconductor test
chip further includes:
a plurality of transistors to measure any temperature gradient in the
semiconductor chip.
39. The semiconductor test chip of claim 23, wherein the semiconductor test
chip further includes:
a plurality of thin gate and thick gate transistor devices for measurement
of temperature or ion contamination of the semiconductor chip.
40. The semiconductor test chip of claim 23, wherein the semiconductor test
chip further includes:
a plurality of resistors for measurement of thermal performance of a
portion of the semiconductor chip and any package in which it is
contained.
41. The semiconductor test chip of claim 23, wherein the semiconductor chip
is substantially square in shape.
42. The semiconductor test chip of claim 23, wherein the semiconductor test
chip further includes:
a plurality of flip chip test pads located substantially in a center
portion of the semiconductor chip.
43. The semiconductor test chip of claim 23, wherein the semiconductor test
chip further includes:
a plurality of flip chip test pads in an array located in substantially a
center portion of the semiconductor chip.
44. The semiconductor test chip of claim 23, wherein the semiconductor test
chip includes:
a plurality of flip chip test pads located in substantially a center of the
semiconductor chip, a portion of the plurality of flip chip test pads
being connected in a daisy chain connection by conductors extending
therebetween, the portion of the plurality of flip chip test pads being
connected in the daisy chain being independent of other flip chip pads of
the plurality of flip chip test pads. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor reliability test chip.
More specifically, the present invention relates to a semiconductor
reliability test chip including a plurality of test functions.
2. State of the Prior Art
Typically, the reliability of semiconductor products has been tested by
operating the semiconductor products in a variety of life accelerating
environments over periods of time until the components fail. Subsequently,
the semiconductor components are inspected and tested electrically in an
attempt to determine the cause of failure. Since there are many reasons
for the failure of semiconductor components, the analysis of failed
components can be lengthy and difficult. Attempts have been made to design
semiconductor test chips or dies to assess a specific type of failure of
the semiconductor component. An article by J. S. Sweet, entitled "The Use
of Special Purpose Assembly Test Chips for Evaluating Reliability In
Packaged Devices", published by Sandia National Laboratory, pages 15-19,
describes some of these types of chips. The article describes a series of
individual special purpose assembly test chips to aid in assessing the
reliability of packaged integrated circuits. The special purpose assembly
test chips contain special purpose circuits or sensors which enhance the
detection of failures or detect moisture, detect mobile ions, or other
contaminants which can lead to failure of the semiconductor component.
In U.S. Pat. No. 5,414,351, a method is described for testing the
reliability of terminals in a semiconductor package by placing a test chip
in the package wherein the test chip has an insulating substrate, a
passivating layer over the metal layer provided with a plurality of
openings, a plurality of Gold (Au) terminals in the openings bonded to the
metal layer and a master ground terminal bonded to the metal layer.
Input/Output (I/O) terminals are provided in the package structure for
each of the Au terminals, master terminals are connected to the I/O
terminals with wire, and the test chip is sealed in a package. The
resistance of each terminal is monitored to determine any change of
electrical resistance, which is an indication of terminal deterioration.
U.S. Pat. No. 5,329,228 discloses a semiconductor test chip for use in
semiconductor fabrication fault analysis comprising an n.times.m array of
transmission gate cells arranged such that, within a given row, respective
strips of conductive material of a first type form common source and drain
electrodes for the transistors of the row. The sources and drains of each
row are independent and within a column of strips of conductive material
of a second type forming common gate electrodes such that each column of
transistors can be turned on independently. The results of the
semiconductor test chip are useful for characterizing process yields and
reliability as well as useful for high level yield modeling.
U.S. Pat. No. 5,326,428 describes a method of engaging electrically
conductive test pads on a semiconductor substrate having integrated
circuitry to test the operability thereof. The patent further describes a
test probe suitable for used with the substrate.
U.S. Pat. No. 5,214,657 describes circuitry to enable dicing of a wafer of
semiconductor chips. The circuitry is included in the street area of the
chips forming the wafer.
U.S. Pat. No. 5,059,899 discloses a method for producing individual
semiconductor chips from wafers, wherein the test pads for the testing of
individual dies or chips are formed in the scribe or street area of the
chip.
U.S. Pat. No. 4,420,722 discloses a technique for testing for heavy metal
contamination in semiconductor processing furnaces through the use of a
specially designed semiconductor chip having a plurality of PN-junctions,
at least one of which is completely isolated from the sides of the chip.
The specially designed semiconductor chip is manufactured to exhibit a
high reverse recovery time which is measured and compared to determine if
it has decreased over time.
U.S. Pat. No. 4,360,142 discloses the use of dummy semiconductor chips in
developing improved solder bonds.
U.S. Pat. Nos. 3,746,973, 3,803,483, and 5,341,685 disclose the use of test
chips to test semiconductor chips or apparatus for use in the testing of
lead tab bonds and semiconductor chips.
In contrast to the prior art, a more compr | | |
