A novel cache coherency protocol provides a modified-unsolicited (M.sub.U) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the M.sub.U state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The M.sub.U state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the M.sub.U state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.
CROSS-REFERENCES TO RELATED APPLICATIONS
The present invention is related to the following applications filed concurrently with this application: U.S. patent application Ser. No. 09/437,178 entitled "MULTIPROCESSOR SYSTEM BUS PROTOCOL WITH COMMAND AND SNOOP RESPONSES FOR MODIFIED-UNSOLICITED CACHE STATE;" U.S. patent application Ser. No. 09/437,177 entitled "MODIFIED-UNSOLICITED CACHE STATE WITH DYNAMIC HARDWARE/SOFTWARE CONTROLLABLE MECHANISM TO OPTIMIZE FOR LOAD IMBALANCE" U.S. patent application Ser. No. 09/437,176 entitled "LOAD INSTRUCTIONS TO ENHANCE MODIFIED-UNSOLICITED CACHE STATE PROTOCOL" U.S. patent application Ser. No. 09/437,180 entitled "PROTOCOL FOR TRANSFERRING MODIFIED-UNSOLICITED STATE DURING DATA INTERVENTION" U.S. patent application Ser. No. 09/437,181 entitled "CACHE ALLOCATION MECHANISM FOR MODIFIED-UNSOLICITED CACHE STATES".
A cache controller expresses a status of a data block by one of six statuses obtained by newly adding Writable Modified to Invalid, Shared, Exclusive, Modified, and Shared Modified. In response to a fetching request from a self system CPU for a data block having the status of Invalid I, when the data block having the status of Modified M is obtained from a cache apparatus of another system, the cache controller changes the status of the obtained data block from Invalid to Writable Modified. The cache controller also switches the status of the data block on the obtaining destination side from Modified to Invalid. As a result, the making of a status change notification to the other system in response to a subsequent storing request from the self system CPU, is unnecessary.
In general, in one aspect, the disclosure describes an apparatus capable to select a queue. The apparatus includes a queue occupancy device to indicate an occupancy status of the queues, a queue occupancy cache to record an update in occupancy status of a particular queue, a next queue selector to select a queue based on said queue occupancy device and a most recently serviced queue, and a queue identification register to identify a most recently serviced queue.
In general, in one aspect, the disclosure describes an apparatus that includes a transmission module to split a data segment into a plurality of data stripes and transmit each data stripe over an associated data channel. The plurality of data channels are organized into at least one group and each group has an associated parity channel to transmit a parity stripe generated based on the data stripes within the group. The apparatus also includes a reception module to receive the plurality of data stripes and the at least one parity stripe. The apparatus further includes a controller to control the operation of the apparatus.
In general, in one aspect, the disclosure describes an apparatus that includes a plurality of flow controllable queues containing data to be transmitted. The queues are organized by flow. The apparatus also includes a plurality of destinations to receive data from the plurality of queues. The apparatus further includes a controller to continually maintain an aggregate count of data ready for transmission to the destinations and determine next queue to transmit data from based at least partially on the aggregate counts.
In general, in one aspect, a switching device is described that includes a segmentation unit to receive packets and divide packets having a length greater than a maximum segment length into multiple segments. A plurality of queues associated with a source and a destination stores the segments. A request generator generates requests that include external factors including amount of data contained in the queue and at least some subset of priority and age. A scheduler receives the requests and assigns the requests an internal priority based on the external factors. The scheduler processes the requests for the queues by internal priority in order to generate grants. A framer, responsive to the scheduler, aggregates a plurality of segments for the queues that received a grant to form a frame and to transmit the frame to an associated destination. The frame may contain segments associated with different packets.
