The capacitor comprises an lower electrode 22, a dielectric film 30 formed on the lower electrode 22, a floating electrode 20 formed on the dielectric film 30, a dielectric film 50 formed on the floating electrode 40 and having a film orientation different from that of the dielectric film 30, and an upper electrode 80 formed on the dielectric film 50, whereby various characteristics depending on film orientations of the dielectric films can be simultaneously improved.

Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n.sup.+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n.sup.+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.

Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n.sup.+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n.sup.+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.

In a ferroelectric memory, there are provided a plurality of word lines, a plurality of bit lines crossing there-with, a plurality of memory cells having ferroelectric capacitors arranged at the positions of these crossovers and a plurality of correction capacitors connectable with the bit lines. At least some of the plurality of correction capacitors are connected with a bit line so as to be capable of increasing bit line capacitance by a prescribed amount.

An IC device has a MOSFET serving as a power switch, a condenser connected between a first input terminal of the IC and the gate of the MOSFET, and a ferroelectric condenser connected between a second input terminal of the IC and the gate of the MOSFET. A prescribed voltage having a predetermined polarity is applied across the first and the second input terminals to generate a remanent polarization oriented in a specific direction in the ferroelectric condenser, thereby raising the threshold voltage of the MOSFET to a higher level than its original level. The power switching MOSFET is fabricated in the same manufacturing process as for other circuit blocks of the IC device such that it has substantially the same threshold voltage as that of the MOSFETs in other circuit blocks.