A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.
CROSS REFERENCE TO RELATED APPLICATIONS
This is continuation of prior U.S. patent application Ser. No. 08/924,518, filed on Sep. 5, 1997, which is hereby incorporated by reference, now abandoned, and priority thereto for common subject matter is hereby claimed.
The present application is related to the following U.S. patent applications:
"METHOD AND APPARATUS FOR INTERFACING A PROCESSOR TO A COPROCESSOR" invented by William C. Moyer et. al., having U.S. application Ser. No. 08/924,508, now U.S. Pat. No. 5,983,338, filed concurrently herewith, and assigned to the assignee hereof; and
"METHOD AND APPARATUS FOR INTERFACING A PROCESSOR TO A COPROCESSOR" invented by William C. Moyer et. al., having U.S. application Ser. No. 08/924,137, now U.S. Pat No. 5,923,893, filed concurrently herewith, and assigned to the assignee hereof.
A method and apparatus for processing security operations are described. In one embodiment, a processor includes a number of execution units to process a number of requests for security operations. The number of execution units are to output the results of the number of requests to a number of output data structures associated with the number of requests within a remote memory based on pointers stored in the number of requests. The number of execution units can output the results in an order that is different from the order of the requests in a request queue. The processor also includes a request unit coupled to the number of execution units. The request unit is to retrieve a portion of the number of requests from the request queue within the remote memory and associated input data structures for the portion of the number of requests from the remote memory. Additionally, the request unit is to distribute the retrieved requests to the number of execution units based on availability for processing by the number of execution units.
In one embodiment, an apparatus comprises a microcontroller unit to store instructions into an execution queue. The apparatus also comprises an execution queue unit to generate a widely decoded functional execution instruction based on at least one instruction stored in the execution queue. Additionally, the apparatus comprises a functional unit to execute the widely decoded functional execution instruction asynchronous to the generation of the widely decoded functional execution instruction.
Method and apparatus for performing distributed processing in a multi-processing unit environment. A first processing unit modifies a complex operation to provide an operational request packet comprising a corresponding simplex operation and remainder. The packet is communicated to a second processing unit which processes the packet to arrive at a result for the complex operation, preferably by arriving at a result for the simplex operation and combining this result with the remainder. In this way, inter-processor operations can be efficiently encoded and distributed to meet the requirements of a given architecture. Preferably, the first processing unit determines the remainder by separately arriving at the result for the complex operation. The complex operation is preferably characterized as a mathematical operation on a non-power of two operand (e.g., 30), and the simplex operation is characterized as a mathematical operation on a power of two operand (e.g., 32).
A system is disclosed comprising a logic circuit in an integrated circuit device, wherein the logic circuit comprises a logic fabric that includes a plurality of configurable logic blocks, switching blocks, and input/output blocks, wherein the logic fabric is configured according to configuration data provided to the integrated circuit device from an external memory and at least a portion of the logic fabric is configured as a configured processor to perform a first fixed logic function according to the configuration data. A fixed logic processor, a first auxiliary processing interface, a second fixed logic processor, a second auxiliary processing interface enable communication with the configured processor, wherein the configured processor remains configured to enable both the fixed logic processor and the second fixed logic processor to access the configured processor to perform the fixed logic function.
